Sacrificial shallow trench isolation oxide liner for...

Details Sacrificial shallow trench isolation oxide liner for... Sacrificial shallow trench isolation oxide liner for...

2007-03-20

2007-03-20

Nhu, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S204000, C257S347000, C257S616000, C257SE21008, C257S092000, C257S115000, C257S585000, C257S632000

Reexamination Certificate

active

10985462

ABSTRACT:
A strained-silicon (Si) channel CMOS device shallow trench isolation (STI) oxide region, and method for forming same have been provided. The method forms a Si substrate with a relaxed-SiGe layer overlying the Si substrate, or a SiGe on insulator (SGOI) substrate with a buried oxide (BOX) layer. The method forms a strained-Si layer overlying the relaxed-SiGe layer; a silicon oxide layer overlying the strained-Si layer, a silicon nitride layer overlying the silicon oxide layer, and etches the silicon nitride layer, the silicon oxide layer, the strained-Si layer, and the relaxed-SiGe layer, forming a STI trench with trench corners and a trench surface. The method forms a sacrificial oxide liner on the STI trench surface. In response to forming the sacrificial oxide liner, the method rounds and reduces stress at the STI trench corners, removes the sacrificial oxide liner, and fills the STI trench with silicon oxide.

REFERENCES:
patent: 6194285 (2001-02-01), Lin et al.
patent: 6600170 (2003-07-01), Xiang
patent: 6677192 (2004-01-01), Fitzgerald
patent: 6696348 (2004-02-01), Xiang
patent: 6723661 (2004-04-01), Fitzergald
patent: 6787423 (2004-09-01), Xiang
patent: 6897122 (2005-05-01), Xiang

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