Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1998-06-23
2001-10-02
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S735000, C438S736000
Reexamination Certificate
active
06297170
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor devices in general, and more particularly to semiconductor devices having anti-reflective coatings to aid in the patterning of a reflective layer thereon to form, for example, a gate electrode. The invention also relates to methods for making a semiconductor having a patterned reflective layer.
The semiconductor industry's continuing drive toward integrated circuits with ever decreasing geometries, coupled with its pervasive use of highly reflective materials, such as polysilicon, amorphous silicon, aluminum, and metal silicides, has led to increased photolithographic patterning problems. Unwanted reflections from these underlying reflective materials during the photoresist patterning process often cause the resulting photoresist patterns to be distorted. This problem is further compounded when photolithographic imaging tools used to generate the photoresist patterns utilize deep ultraviolet (DUV) exposure wavelengths (such as approximately 300 nanometers (nm) or less). Although shorter imaging wavelengths bring improved resolution by minimizing diffraction limitations, the resulting patterns generated in the photoresist are often compromised by the effects of unwanted reflections from underlying reflective materials which tend to increase at these shorter wavelengths.
A reflective layer in, for example, a transistor, whether a metal or a semiconductor, must be patterned to define various lines, contacts, gates, etc. within the transistor device. In conventional patterning, a resist layer, such as a photoresist, is deposited on, or over, the reflective layer. A lithography mask (also referred to herein as a “pattern projection mask”) having a pattern corresponding to the desired pattern of, for example, the gate electrode is then placed over the substrate. Radiation is transmitted through transparent portions of the pattern projection mask and into the resist layer to thereby alter portions of the resist layer exposed to the radiation. Ideally, only those portions of the resist layer directly beneath the transparent portions of the pattern projection mask will be altered.
Some radiation, however, is transmitted through the resist layer and will be reflected by an underlying reflective layer. The extent of reflection of this radiation is dependent upon the geometry and optical properties of the underlying layer. The radiation reflects back into the resist layer, and in some cases undesirably undercuts the opaque portions of the mask by reflecting into regions other than those directly beneath the transparent portions of the mask.
Upon developing, the resist layer will have a pattern which does not exactly match the lithography mask pattern due to the reflective radiation exposure of portions of the resist layer which should have been protected by opaque portions of the mask, but were not due to this undercutting. The inconsistency in the pattern is then replicated into the device through subsequent processing. In many instances, the replication of an inaccurate resist layer into a reflective layer results in notches in lines formed from the reflective layer. Accordingly, this problem is often referred to as “reflective notching.”
Because of the demands on critical dimension and depth of focus control, there have been proposed in the prior art a number of methods for overcoming these patterning problems; however, to date none have proven satisfactory. Perhaps the most widely accepted method is the use of an anti-reflective coating (ARC). Such an ARC is commonly used to aid in the patterning of deep submicron gate electrodes for field effect transistor applications. ARCS are typically placed beneath the photoresist layer and therefore are commonly referred to as bottomside anti-reflective coatings (BARCs). Many types of BARCs have been used in the prior art, including, for example, SiON.
When a BARC is used, for example, in the patterning of a gate electrode, it is placed over the reflective layer, masked with a photoresist, and etched to expose the underlying gate electrode. Another process is then used to finish etching the gate electrode, before or after stripping the photoresist. A problem commonly encountered when ARCs are used in this way is that materials used therein tend to be unstable during furnace exposure and therefore need to be removed before subsequent processing steps may be undergone. Additionally, silicidation of the surface of a polysilicon gate electrode patterned in this way generally requires ARC removal. However, with the sides of the gate electrode and the surface of the gate oxide exposed, removing ARCs is not straightforward. Attempting to remove an ARC with wet chemicals or plasma may lead to damage of the gate or gate oxide.
In view of this background, there is a great need for anti-reflective coatings which are better suited for use in making semiconductor devices due to excellent thermal stability and/or selective removability. Such anti-reflective coatings are provided by the present invention, wherein inventive anti-reflective coatings may be used as sacrificial hardmasks, preferably for field effect transistor gate formation.
SUMMARY OF THE INVENTION
The present invention relates to semiconductor devices in general, and more particularly to semiconductor devices having anti-reflective coatings to aid in the patterning of a reflective layer thereon to form a patterned reflective layer such as, for example, a gate electrode. The invention also relates to methods for making a semiconductor having a patterned reflective layer. While the actual nature of the invention covered herein can only be determined with reference to the claims appended hereto, certain features which are characteristic of the preferred embodiments disclosed herein are described briefly as follows.
In one aspect of the invention, there is provided a method for forming one or more semiconductor devices. A device is formed by first depositing a reflective layer on a semiconductor substrate and then forming a multilayer anti-reflective coating (“ARC”) having a first layer and a second layer, wherein the first layer comprises a different composition than the second layer. The first layer of the ARC is positioned between the reflective layer and the second layer. Next, a resist layer is deposited such that the second layer is positioned between the first layer and the resist layer, and selected portions of the resist layer are exposed to electromagnetic radiation. After the resist layer is selectively exposed, it is developed to create a resist mask, the resist mask defining a first region and a second region of the anti-reflective coating and a first region and a second region of the reflective layer. The first region of the anti-reflective coating and the first region of the reflective layer lie between the resist mask and the substrate, and the second region of the anti-reflective coating and the second region of the reflective layer comprise the portions of the layers which do not lie between the resist mask and the substrate. The second region of the ARC is then removed to expose the second region of the reflective layer. Finally, the resist mask, the first region of the second layer and the second region of the reflective layer are removed to produce a patterned reflective layer having a first layer mask thereon.
According to another aspect of the invention, there is provided a method for forming one or more semiconductor devices by first providing a workpiece comprising a semiconductor substrate, a reflective layer, a multilayer anti-reflective coating having a first layer and a second layer, and a resist layer. The reflective layer is positioned between the substrate and the anti-reflective coating, the first layer is positioned between the reflective layer and the second layer, and the second layer is positioned between the first layer and the resist layer. Selected portions of the resist are then exposed to electromagnetic radiation and the resist layer is developed to create a resist mask which
Gabriel Calvin Todd
Haskell Jacob
Sethi Satyendra
Meier Stephen D.
VLSI Technology Inc.
Vockrodt Jeff
Woodard Emhardt Naughton Moriarty & McNett
LandOfFree
Sacrificial multilayer anti-reflective coating for mos gate... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Sacrificial multilayer anti-reflective coating for mos gate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sacrificial multilayer anti-reflective coating for mos gate... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2598017