Sacrificial feature for corrosion prevention during CMP

Details Sacrificial feature for corrosion prevention during CMP Sacrificial feature for corrosion prevention during CMP

2002-05-17

2004-09-07

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S692000, C438S690000, C438S687000, C438S622000, C438S959000, C257S758000, C257S784000, C257S786000, C257S081000, C257S082000

Reexamination Certificate

active

06787470

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to chemical-mechanical polishing (CMP), and more particularly to the corrosion that can result from using CMP.
BACKGROUND OF THE INVENTION
Chemical mechanical polishing (CMP) is a semiconductor wafer flattening and polishing process that combines chemical removal with mechanical buffing. It is used for polishing and flattening wafers after crystal growing, and for wafer planarization during the wafer fabrication process. CMP is a favored process because it can achieve global planarization across the entire wafer surface, can polish and remove all materials from the wafer, can work on multi-material surfaces, avoids the use of hazardous gasses, and is usually a low-cost process.
Via holes, or more simply “vias,” are semiconductor device features that are through holes made in a substrate, for a variety of different purposes. Via holes may be used to ground semiconductor devices and passive devices. Via holes may be made through dielectric layers, for subsequent metal deposition to form a plug and create an interconnect between two metal lines. Multi-level interconnect schemes may employ such via holes. Processes used to perform such interconnection using via holes include the damascene process and the dual-damascene process.
In the damascene process, interconnect metal lines are delineated in dielectrics, isolating them from each other using CMP in lieu of lithography and etching. The interconnect pattern is first lithographically defined in the dielectric layer, and then metal is deposited to fill the resulting trenches. Excess metal is removed by CMP. The dual-damascene process is a modified version of the damascene process, and is also used to form metal interconnect geometries using CMP instead of metal etching. In the dual-damascene process, two inter-layer dielectric patterning steps and one CMP step creates the pattern that would require two patterning steps and two metal CMP steps if the conventional damascene process were instead used.
Thus, the fundamental difference of damascene processing relative to standard processing is that metal lines are not etched, but deposited in grooves within the dielectric layer, and excess metal is removed by CMP. Both damascene process are considered the future technology of choice for laying metal lines and interconnects on semiconductor devices. The damascene process is commonplace for 0.18-0.13 micron technology, whereas the dual-damascene process is more common for 0.13-0.10 micron technology.
A problem with the CMP as performed in damascene and other processes is that corrosion can result, particularly at the ends of copper interconnects. More specifically, some semiconductor layouts are more vulnerable to such corrosion. These layouts may have one or more of the following characteristics. First, the end of an interconnect has a small geometric tip. Second, the interconnect has an unbalanced geometric pattern, including a long metallic line with sufficient resistance. An unbalanced geometric pattern can be generally defined herein as including a long line with one or more tips extending therefrom. The charge induced during CMP gathers at the tip of the end of the long metallic line. This results in a strong electric field at the line tip, causing a chemical-electrical reaction at the tip. The chemical-electrical reaction results from the CMP solution and the interconnect itself. Ends of the unbalanced interconnect act as the anode and cathode for this reaction.
FIG. 1
shows an example of a semiconductor layout
100
that is susceptible to copper interconnect corrosion resulting from performing CMP. The layout
100
includes a number of metal lines, such as the metal line
102
, as well as a number of unused, or “dummy,” metal lines, such as the metal line
104
. The probe pad
106
has a metal interconnect
108
extending therefrom. The metal interconnect
108
, which may be a copper interconnect, itself has two tips
110
extending therefrom. These tips
110
may be vias, or another semiconductor feature. During CMP, these tips
110
are susceptible to corrosion, for the reasons described in the preceding paragraph.
Whereas
FIG. 1
is a top view of the semiconductor layout
100
,
FIG. 2
shows a partial side view of the semiconductor layout
100
, including a dielectric
202
. The tips
110
are shown as vias, extending to the metal interconnect
108
. Again, the tips
110
may be corroded during CMP.
FIG. 3
shows another view of a semiconductor layout
300
that is susceptible to copper interconnect corrosion resulting from performing CMP.
FIG. 3
specifically shows a top view of the layout
300
, where there is a large metallic pad
302
, from which a metallic line or interconnect
306
extends and ends at a small stacked via and metal island
304
. The metallic line or interconnect
306
has sufficient resistance, as indicated by the springed line
308
, that corrosion of the small stacked via and metal island
304
results.
Therefore, there is a need for preventing corrosion during CMP. Such corrosion should specifically be prevented for features that are particularly susceptible to corrosion. These features at least include unbalanced interconnect layouts as have been shown and described. For these and other reasons, there is a need for the present invention.
SUMMARY OF THE INVENTION
The invention relates to a sacrificial semiconductor feature for preventing corrosion that can result during chemical-mechanical planarization (CMP). A semiconductor device of the invention is fabricated at least in part by performing CMP. The device includes a desired semiconductor feature and a sacrificial semiconductor feature. The desired semiconductor feature may have an unbalanced geometric pattern that includes a metallic line ending in at least one tip. The at least one tip is susceptible to corrosion resulting from performing CMP. The sacrificial semiconductor feature is preferably located off the metallic line of the desired semiconductor feature. The sacrificial semiconductor feature attracts charge induced during CMP that is otherwise attracted by the at least one tip of the desired semiconductor feature. The presence of the sacrificial semiconductor feature thus substantially prevents corrosion of the desired semiconductor feature, including its tip(s).
Embodiments of the invention provide for advantages over the prior art. As has been indicated, the presence of the sacrificial semiconductor feature prevents corrosion of the desired semiconductor feature. Thus, the sacrificial semiconductor feature is itself sacrificed by being corroded, so that the desired semiconductor feature is not corroded. Charge that would otherwise be induced at the desired semiconductor feature is instead induced at the sacrificial semiconductor feature, sparing the desired semiconductor feature from corrosion. The sacrificial semiconductor feature may be antenna-shaped or needle shaped tips, and there may be more than one sacrificial semiconductor feature and more than one desired semiconductor feature. The sacrificial semiconductor feature may include one or more vias that may or may not have corresponding metal islands therein. Other advantages, embodiments, and aspects of the invention will become apparent by reading the detailed description that follows, and by referencing the attached drawings.


REFERENCES:
patent: 6376345 (2002-04-01), Ohashi et al.
patent: 6515366 (2003-02-01), Chiou et al.
patent: 2002/0079517 (2002-06-01), Kim

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