Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-03-12
2001-04-17
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S223000, C327S208000
Reexamination Certificate
active
06218879
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of digital circuits. More particularly, this invention relates to S-R flip-flop circuits.
2. Description of the Prior Art
It is known to provide so-called S-R flip-flop circuits of various forms. An S-R flip-flop circuit classically has the behavior that the output goes high when the set input goes high and the output goes low when the reset input goes high. Within this behavior, it will be appreciated that the inputs may also be used in their complementary form to achieve similar behavior if this is appropriate. Furthermore, the inputs can be either level sensitive or edge-triggered. Different types of S-R flip-flop are appropriate in different circumstances. In some circumstances, edge-triggered input behavior is desirable to avoid problems due to potentially conflicting inputs and to provide more predictable behavior.
Within the field of digital circuits it is a general objective to seek to make the circuits using few gates and to make the circuits operate quickly. Measures that assist towards these objectives are strongly desirable.
SUMMARY OF THE INVENTION
Viewed from one aspect the present invention provides an S-R flip-flop circuit comprising:
(i) a first signal input for receiving a first input signal having a signal value of either A or B;
(ii) a second signal input for receiving a second input signal having a signal value of either C or D;
(iii) an output signal node bearing an output signal having a signal value of either E or F;
(iv) an internal node bearing an internal signal having a signal value of either G or H;
(v) a first stack of gates responsive to said output signal and said first input signal; and
(vi) a second stack of gates responsive to said internal signal, said first input signal and a second input signal, said internal node being between said first stack of gates and said second stack of gates; wherein
(vii) said first stack of gates forces said internal signal to G (
0
) when said first input signal is A (
1
) and said output signal is E (
1
) and said first stack of gates forces said internal signal to H (
1
) when said first input signal is B (
0
) and said output signal is F (
0
);
(viii) said second stack of gates forces said output signal to F (
0
) when said internal signal is G (
0
) and said first input signal is B (
0
), whereby
(ix) when said output signal is E (
1
) and said first input signal is A (
1
), said internal signal will be G (
0
) and a transition in said first signal from A (
1
) to B (
0
) will force said output signal to transition from E (
1
) to F (
0
) followed by said internal signal being forced to transition from G (
0
) to H (
1
), thereby effecting an edge-triggered change in said output signal from E (
1
) to F (
0
) in response to said first input signal changing from A (
1
) to B (
0
).
The invention provides an S-R flip-flop circuit that exhibits edge-triggered behavior on at least one of its inputs whilst requiring the use of relatively few gates and incurring relatively few gate delays in its operation.
In order to improve the stability and reliability of the circuit it is desirable to include level holding circuits for maintaining both the internal signal and the output signal.
As mentioned above, the invention provides at least one edge-triggered input. If level sensitive behavior is required for the second input then this may be achieved in embodiments in which said second stack of gates is responsive to said second input signal to force said output signal to E when said second input signal is A independent of said internal signal or said first input signal. With such embodiments it is important that certain restrictions are imposed upon the states that may be adopted by the inputs in order to avoid excessive current flow within the circuit.
If edge-triggered behavior is required for both inputs, then this may be achieved in embodiments including a further internal node bearing a further internal signal having a signal value of either I or J; and
a third stack of gates responsive to said output signal and said second input signal; wherein
said second stack of gates is also responsive to said further internal signal, said further internal node being between said first stack of gates and said second stack of gates;
said third stack of gates forces said further internal signal to I (
0
) when said second input signal is C (
1
) and said output signal is E (
1
) and said third stack of gates forces said further internal signal to J (
1
) when said second input signal is D (
0
) and said output signal is F (
0
);
said second stack of gates forces said output signal to E (
1
) when said further internal signal is J (
1
) and said second input signal is C (
1
), whereby
when said output signal is F (
0
) and said second input signal is D (
0
), said further internal signal will be J (
1
) and a transition in said second signal from D (
0
) to C (
1
) will force said output signal to transition from F (
0
) to E (
1
) followed by said further internal signal being forced to transition from J (
1
) to I (
0
), thereby effecting an edge-triggered change in said output signal from F (
0
) to E (
1
) in response to said second input signal changing from B (
0
) to C (
1
).
The various stacks of gates can be conveniently provided by a stack of field effect transistors (FETs) in series between a supply voltage source and a ground voltage source. In the context of the invention the number of series field effect transistors is not too large as to cause problems due to voltage drop along the stack.
The above, and other objects, features and advantages of this invention will be apparent from the following detailed description of illustrative embodiments which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 4806786 (1989-02-01), Valentine
patent: 4825100 (1989-04-01), Caspell
patent: 5095225 (1992-03-01), Usui
patent: 5208487 (1993-05-01), Matsuura et al.
patent: 5604456 (1997-02-01), Nitta
ARM Limited
Lam Tuan T.
Nguyen Hai L.
Nixon & Vanderhye P.C.
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