Rush current suppression circuit

Details Rush current suppression circuit Rush current suppression circuit

2002-03-26

2004-04-06

Reichard, Dean A. (Department: 2831)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Impedance insertion

C361S056000, C361S093300, C361S119000, C361S106000, C323S222000, C323S282000

Reexamination Certificate

active

06717784

ABSTRACT:

BACKGROUND OF THE INVENTION
This application claims the benefit of a Japanese Patent Application No.2001-323281 filed Oct. 22, 2001, in the Japanese Patent Office, the disclosure of which is hereby incorporated by reference.
1. Field of the Invention
The present invention generally relates to rush current suppression circuits, and more particularly to a rush current suppression circuit for a power supply.
In electronic equipments which handle electronic information, there are demands to reduce voltages and to increase currents, in large scale integrated circuits (LSIs). In addition, there are demands to reduce the size and to improve the efficiency of power supply units which supply power to such LSIs.
2. Description of the Related Art
FIG. 1
is a circuit diagram showing an example of a conceivable rush current suppression circuit. In
FIG. 1
, Ei denotes an input power supply or input power supply voltage, Ec denotes an output voltage, and a reference numeral
1
denotes a load with respect to a power supply circuit. In the power supply circuit, a field effect transistor FET
1
is inserted in series to a loop of the circuit, a resistor R
1
has one end thereof connected to an output line, and a Zenner diode ZD
1
is connected in series to the resistor R
1
. An anode of the Zenner diode ZD
1
is connected to a gate G of the transistor FET
1
.
A smoothing capacitor C
1
is connected to an output end of the power supply Ei. A rapid discharge and delay circuit
2
has one end thereof connected to the anode of the Zenner diode ZD
1
, and the other end thereof connected to a common line of the power supply Ei.
The rapid discharge and delay circuit
2
includes a diode D
1
, a transistor TR
1
having an emitter thereof connected to a cathode of the diode D
1
, a resistor R
3
connected between a collector of the transistor TR
1
and the common line, and a resistor R
2
having one end thereof connected to a base of the transistor TR
1
and the other end thereof connected to the common line. The base of the transistor TR
1
and an anode of the diode D
1
are connected by a node which connects to the anode of the Zenner diode ZD
1
.
A description will now be given of the operation of the power supply circuit shown in
FIG. 1
, by referring to FIG.
2
.
FIG. 2
is a timing chart for explaining signal waveforms at various parts of the circuit shown in FIG.
1
. In
FIGS. 2
, (a) shows the input power supply voltage Ei, (b) shows the output voltage Ec, (c) shows a voltage VC
2
applied to the capacitor C
2
(or a gate voltage VGS of the transistor FET
1
), and (d) shows a load current Ii.
(1) When Input Power Supply Voltage Ei Is Applied:
When the input power supply voltage Ei is applied to the circuit at a time t
1
as shown in FIG.
2
(
a
), the input power supply voltage Ei is applied to the gate G of the transistor FET
1
via the resistor R
1
and the Zenner diode ZD
1
. At the same time, the voltage VC
2
applied on the capacitor C
2
of the rapid discharge and delay circuit
2
gradually increases as shown in FIG.
2
(
c
) because charges are gradually supplied to the capacitor C
2
. The voltage VC
2
of the capacitor C
2
is applied to the transistor FET
1
as the gate voltage VGS.
When the gate voltage VGS exceeds a level which turns the transistor FET
1
ON at a time t
2
, the transistor FET
1
turns ON as shown in FIG.
2
(
b
). Hence, a rush current is suppressed by turning ON the transistor FET
1
after a delay time from the time t
1
when the input power supply voltage Ei is applied. As a result, a charging current starts to flow to the smoothing capacitor C
1
, and the output voltage Ec increases as shown in FIG.
2
(
b
). Consequently, an excessively large rush current flows as the load current Ii, as shown in FIG.
2
(
d
).
(2) When Instantaneous Cutoff of Input Power Supply (Instantaneous Short-Circuit Failure of Input Power Supply Ei) Occurs:
At a time t
3
shown in FIG.
2
(
a
), both ends of the input power supply Ei are short-circuited and the input power supply voltage Ei becomes zero. In this state, the charge accumulated in the smoothing capacitor C
1
is discharged. A discharge loop of this discharge includes the input power supply Ei and an internal diode of the transistor FET
1
, that is, a body diode of the transistor FET
1
indicated by a dotted line in FIG.
1
. When the charge of the smoothing capacitor C
1
is discharged, a peak current flows in a reverse direction as shown in FIG.
2
(
d
) in the load current Ii at the time of the instantaneous cutoff of the input power supply Ei.
At the same time, when the charged voltage of the smoothing capacitor C
1
becomes less than or equal to a Zenner voltage of the Zenner diode ZD
1
, the transistor TR
1
of the rapid discharge and delay circuit
2
turns ON. Hence, the rapid discharge and delay circuit
2
operates as a rapid discharge circuit, and rapidly discharges the charge accumulated in the capacitor C
2
. As a result, the gate voltage VGS is rapidly discharged to zero as shown in FIG.
2
(
c
), to thereby turn OFF the transistor FET
1
.
(3) When Input Power Supply Resumes Power:
It is assumed that the power of the input power supply Ei resumes power from a time t
4
. Since the voltage applied across both ends of the smoothing capacitor C
1
is approximately zero in this state, the operation from the time t
4
when the input power supply Ei resumes power becomes the same as the operation when the input power supply voltage Ei is newly applied. Accordingly, a voltage having the same voltage as the input power supply Ei is applied to the smoothing capacitor C
1
, and the rush current having the same value as the case (1) described above flows.
At the time of the instantaneous cutoff of the input power supply Ei, the charge accumulated in the smoothing capacitor C
1
is discharged via the discharge loop via the body diode of the transistor FET
1
, to thereby rapidly reduce the charge of the capacitor C
1
. For this reason, when the input power supply Ei resumes power, the input power supply voltage Ei is directly applied to the smoothing capacitor C
1
when the input power supply Ei resumes power, and the excessively large rush current flows. The flow of such an excessively large rush current is undesirable for the input power supply Ei and for the electronic equipments which uses the input power supply Ei. There is also a possibility that the rush current will affect other apparatuses undesirably.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel and useful rush current suppression circuit in which the problems described above are eliminated.
Another and more specific object of the present invention is to provide a rush current suppression circuit which prevents an excessive decrease in a voltage of a smoothing capacitor, and prevent flow of an excessively large current.
Still another object of the present invention is to provide a rush current suppression circuit adapted to a power supply circuit which includes a common line and an input voltage detection circuit and supplies power from an input power supply via a switching circuit, comprising a smoothing capacitor coupled to an output end of the power supply circuit; and a rapid discharge and delay circuit, coupled to the input voltage detection circuit, carrying out a rapid discharge and a time delay and controlling the switching circuit, where the switching circuit includes first and second field effect transistors which are coupled in series to the common line of the power supply circuit, and the first and second field effect transistors have sources which are coupled to each other and gates which are coupled to each other and driven by the rapid discharge and delay circuit. According to the rush current suppression circuit of the present invention, it is possible to prevent an excessive decrease in a voltage of the smoothing capacitor, and prevent flow of an excessively large current.
A further object of the present invention is to provide a rush current suppression circuit connectable to a power

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