Running-average/decimation filter for an oversampling A/D conver

Details Running-average/decimation filter for an oversampling A/D conver Running-average/decimation filter for an oversampling A/D conver

1993-06-15

1994-07-19

Mai, Tan V.

Boots, shoes, and leggings

3647241, 341166, G06F 1531

Patent

active

053315839

ABSTRACT:
A filter processing unit 2 receives the output of an oversampling-type analog/digital (A/D) converter circuit 1. Predetermined information is acquired by a compensation circuit 3-1 with predetermined timing from the filter processing unit 2 in the course of processing for producing a filter output for a predetermined integration-phase state and the predetermined information is fed back to the filter processing unit 2 as compensation information representing a difference in magnitude between a filter output with an integration phase lagging behind or leading ahead of the predetermined integration-phase state and a filter output with an unchanged integration phase in order to produce a controllable-phase filter output DMout. The timing for the acquisition of the compensation information by the compensation circuit 3-1 is controlled by a control circuit 7-1.

REFERENCES:
patent: 4983975 (1991-01-01), Sugino et al.
1985 IEEE International Solid-State Circuits Conference, "MOS ADC-Filter Combination That Does Not Require Precision Analog Components", Hauser et al., pp. 80-81.
1986 IEEE International Solid-State Circuits Confernece, "A Voiceband 15b Interpolative Converter Chip Set", Yamakida et al., pp. 180-181.
IEEE Journal of Solid-State Circuits, vol. SC-21, No. 6, Dec. 1986, "A 12-bit Sigma-Delta Analog-to-Analog Converter with a 15-MHz Clock Rate", Koch et al., pp. 1003-1010.

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