Run-time reconfigurable testing of programmable logic devices

Details Run-time reconfigurable testing of programmable logic devices Run-time reconfigurable testing of programmable logic devices

2002-01-17

2003-12-23

Barlow, John (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C716S030000, C326S038000, C326S039000, C326S041000, C714S725000, C714S727000

Reexamination Certificate

active

06668237

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to testing circuitry of programmable logic devices (PLDs), and more particularly to testing PLDs in a run-time reconfigurable computing arrangement.
BACKGROUND
The methods and tools used to test programmable logic devices (PLDs) are currently very similar to those used in testing other types of integrated circuit devices. For example, standard commercially available test machines are used to test the PLDs. The PLDs are configured and then tested using test vectors. The test vectors are written to the device via device input pins and test results are extracted via device output pins. The output data are then compared to expected result data to verify correct operation of the configured PLD.
Some PLDs, for example field programmable gate array (FPGA) devices, have a wide variety of configurable resources, which makes testing time consuming. Given the variety of configurable resources, no single configuration is sufficient to exercise all the capabilities of the device. Thus, many reconfigurations of the PLD are performed, and new test vectors are used with each new configuration. Not only are current test methods time-consuming, but the limited bandwidth of the device constrains the ability to move test vectors into and retrieve results data from the device. Furthermore, once a fault or defect is detected, it may take many additional iterations to isolate the fault to a particular resource.
Built-in self test (BIST) approaches include storing the test vectors and results analysis logic in the PLD, which addresses PLD bandwidth issues. However, the BIST approach consumes PLD memory for storage of test vectors and results data at the expense of other potential uses. In addition, the location of the BIST circuitry must itself be defect-free, and special software is required to interface with the BIST circuitry.
The traditional and BIST approaches to testing PLDs each have different advantages but also have certain disadvantages. The traditional approach uses standard tools and methodologies and requires no changes to the PLD hardware, which reduces the learning required to construct a test for a device. The disadvantage is that the traditional approach is better suited to a production environment than an application environment. The BIST approach provides the flexibility of testing a PLD in an application environment. However, special test circuitry must be designed into the PLD, which may consume more than an inconsequential portion of device resources.
A system and method that address the aforementioned problems, as well as other related problems, are therefore desirable.
SUMMARY OF THE INVENTION
In various embodiments, the present invention tests the circuitry of a programmable logic device (PLD). A host data processing arrangement is configured with a run-time reconfiguration programming interface, and a run-time reconfiguration test program that invokes methods of the interface executes on the host arrangement. In response to a method of the programming interface invoked from the test program, the PLD is configured with a first configuration bitstream. State data are then read back from the PLD in response to a method of the programming interface invoked from the test program. The test program also identifies differences between the state data and expected-results data.
Various other embodiments are set forth in the Detailed Description and Claims which follow.


REFERENCES:
patent: 6453456 (2002-09-01), Price
Prasanna Sundararajan, Scott McMillan and Steven A. Guccione, Entitled: “Testing FPGA Devices Using JBits”, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, Dated: Sep. 11-13, 2001, MAPLD 2001. pp. 1-8.

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