Run level pair buffering for fast variable length decoder circui

Details Run level pair buffering for fast variable length decoder circui Run level pair buffering for fast variable length decoder circui

1997-05-30

1999-05-11

Britton, Howard

Television

Bandwidth reduction system

Data rate reduction

A04N7/30

Patent

active

059033118

ABSTRACT:
A decoding circuit for decoding (or decompressing) compressed video data includes an RL circuit, such as MPEG encoded video data. The RL circuit includes a buffer memory for storing run-level pairs during the decoding process. Because the buffer memory in the RL circuit can store ran-level pairs, Huffman-decoding and header decoding, performed by a variable length decoding (VLD) circuit, is decoupled from inverse discrete transform decoding, performed by an IDCT circuit. This decoupling speeds up the decoding pipeline by allowing more continuous operation by both the VLD and IDCT circuits.

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patent: 5481553 (1996-01-01), Suzuki
patent: 5515388 (1996-05-01), Yagasaki
patent: 5668599 (1997-09-01), Cheney

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