Run length limited encoding/decoding system for low power disk d

Details Run length limited encoding/decoding system for low power disk d Run length limited encoding/decoding system for low power disk d

1991-10-31

1994-09-20

Logan, Sharon D.

Coded data generation or conversion

Digital code to digital code converters

To or from run length limited codes

341 57, 341100, 341101, H03M 746, H03M 720

Patent

active

053493508

ABSTRACT:
The run length limited encoding/decoding system of this invention includes a clock swap logic circuit, a read reference clock multiplexer circuit, a write clock skip logic circuit, an encoder start logic circuit, an encoder circuit, a read clock skip logic circuit, a decoder start logic circuit, a decoder circuit, an input data buffer and a three-state output data buffer. The encoder circuit includes a deserializer for receiving serial data from a disk controller and blocking the data into m bit words. Each m bit data word is supplied directly to an encoding combinatorial logic circuit which in turn generates an n bit code word. The n bit code word is loaded in a serializer and serially transmitted out of the serializer. The decoder circuit includes a deserializer/serializer and a decoding combinatorial logic circuit. The deserializer/serializer receives a serial stream of encoded data and converts the data into n bit code words. Each n bit code word is loaded directly into the decoding combinatorial logic circuit which in turn generates an m bit data word. The m bit data word is loaded into the deserializer/serializer so that as the next n bit code word is serially loaded in the deserializer/serializer, the m bit data worded is serially moved out of the deserializer/serializer.

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T. Horiguchi and K. Morita, "An Optimization of Modulation Codes in Digital Recording" IEEE Trans. Magn., vol. MAG-12, p. 740-742, Nov., 1976.

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