Rule inference and localization during synthesis of logic circui

Details Rule inference and localization during synthesis of logic circui Rule inference and localization during synthesis of logic circui

1989-06-28

1992-03-10

Lall, Parshotam S.

Boots, shoes, and leggings

364488, 395921, G06F 1560

Patent

active

050954415

ABSTRACT:
A logic method for accessing rules in a logic circuit synthesis system. Application of rules in a data base results in replacement of one or more model instances with other model instances or in alteration of values associated with the model instances or in the alteration of parameter values in the data base. Model instances are designated as VISIBLE or INVISIBLE, INVISIBLE model instances are ignored during logic circuit synthesis. VISIBLE model instances may be NEW or INACTIVE. All VISIBLE model instances are initially NEW. If no rule assciated with a model instance is TRUE, the model instance becomes INACTIVE. If at least one rule associated with a model instance is TRUE, one or more model instances are replaced and all inserted model instances and model instances directly connected to the inserted model instances become NEW. The number of model instances a rule will replace is called a SIZEWIN value of the rule. During synthesis, each VISIBLE, NEW model instance is paired with its associated rule having the greatest SIZEWIN value. The instance-rule pairs are grouped by SIZEWIN value and the rules of the groups having the greatest SIZEWIN value are tested first. If a model instance has been replaced by a previously executed rule, it is designated as DELETED and its associated, paired rule evaluates to FALSE.

REFERENCES:
patent: 4510616 (1985-04-01), Lougheed et al.
patent: 4554631 (1985-11-01), Reddington
patent: 4613940 (1986-09-01), Shanton et al.
patent: 4656603 (1987-04-01), Dunn
patent: 4700317 (1987-10-01), Watanabe et al.
patent: 4703435 (1987-10-01), Darringer et al.
patent: 4922432 (1990-05-01), Kobayashi et al.
patent: 4937755 (1990-06-01), Yokota et al.
Shinsha et al., "Incremental Logic Synthesis Through Gate Logic Structure Identification", 23rd Design Automation Conference, 1986, pp. 391-397.
Friedman et al., "Quality of Design from an Automatic Logic Generator (ALERT)," IEEE 1970, 7th Design Automation Conf., p. 71.
Friedman et al., "Methods Used in an Automatic Logic Design Generator (ALERT)," IEEE Trans. Computer, vol. C-18, No. 7, Jul. 1969, pp. 593-613.
Darringer et al., "Logic Snythesis Through Local Transformation", IBM Journal, vol. 25, No. 4, Jul. 1981, pp. 272-280.
Darringer et al., "A New Look at Logic Synthesis", IEEE 1980 17th Design Automation Conf., pp. 543-548
"Diverse Design Tools Break into Logic-Synthesis Arena", System Technology, Computer Design, Oct. 15, 1987, pp. 20-21.

Affiliated with

Also associated with

Rating

Rule inference and localization during synthesis of logic circui does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Rule inference and localization during synthesis of logic circui, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Rule inference and localization during synthesis of logic circui will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2289551