Rule based floorplanner

Boots – shoes – and leggings

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Details

364488, 395921, G06F 1500

Patent

active

053114434

ABSTRACT:
A rule based floorplanner for a macrocell array having a plurality of predetermined macrocells. The floorplanner uses a net list (23), a macrocell list (26), and a list of design constraints (31) and characteristics of the base array itself to derive an initial Burain score. A trial floorplan is attempted (33) and checked against a list of theoretical rules (39) and a list of empirical rules (38) to determine a measured Burain score (36) which accurately indicates the difficulty which can be expected when completing the design.

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Ferry, "Interconnection Lengths and VLSI", IEEE Circuits and Devices, Jul. 1985, pp. 39-42.
Hamada et al., "An Efficient Multilevel Placement Technique Using Hierarchical Partitioning", IEEE Transactions on Circuits and Systems, Jun. 1992, pp. 432-439.
D. Ferry, "Interconnection Lengths and VLSI", IEEE Circuits and Devices Magazine, Jul. 1985.

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