Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1998-05-12
2001-04-17
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S735000, C438S738000
Reexamination Certificate
active
06218310
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor devices and manufacturing processes, and more particularly to methods for treating a deep-ultraviolet (deep-UV) configured resist mask prior to etching at least one underlying layer through the resist mask to form a gate or other device feature in a semiconductor device.
BACKGROUND ART
A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of device and circuit features. As the devices and features shrink, new problems are discovered that require new methods of fabrication and/or new arrangements.
FIG. 1
depicts a cross-section of a portion
10
of a conventional semiconductor wafer that has been prepared for selective patterning of at least one semiconductor device feature. As shown, portion
10
includes a substrate
12
, a feature layer
14
, and a resist mask
16
that forms windows
17
a-c.
Substrate
12
is typically a selectively patterned and/or doped semiconductor material having one or more active regions (not shown) that are integral to the semiconductor device. By way of example, if the semiconductor device is a metal oxide semiconductor (MOS) transistor, then the substrate
12
typically includes an active source region, an active drain region, and one or more isolating regions. Feature layer
14
, in this case, typically includes a tunnel oxide layer over which at least one electrically conductive layer, for example, polysilicon, is deposited and subsequently patterned to form at least one gate using conventional fabrication techniques. Resist mask
16
typically includes an organic spin-on compound that is selectively exposed to deep-UV radiation and further processed to reveal specific portions of the top surface
15
of feature layer
14
through windows
17
a-c
, for example.
In order to selectively pattern feature layer
14
, portion
10
(i.e., the semiconductor wafer) is normally placed in an etching tool (not shown) and exposed to a plasma that contains reactive and/or ionized species of gas molecules which chemically react and/or physically bombard the exposed portions of feature layer
14
. For example,
FIG. 2
depicts portion
10
following exposure to a plasma
18
that has removed, or etched away, portions of feature layer
14
to create etched openings
20
a
,
20
b
and
20
c
through windows
17
a
,
17
b
and
17
c
, respectively. Etched openings
20
a
-c extend through feature layer
14
to reveal portions of top surface
13
of underlying substrate
12
.
Resist mask
16
, having served its function is then removed, or stripped away, using conventional techniques.
FIG. 3
depicts portion
10
after resist mask
16
has been stripped away. As shown, a plurality of device features
14
a-d
have been selectively formed from feature layer
14
. Device features
14
a-d
, for example, can be gates of MOS transistors.
Controlling the resulting size and/or shape of a device feature (e.g.,
14
b
) is often critical to functioning of the applicable device. For example, in certain semiconductor devices it is preferred that the design feature have substantially planar and/or vertical sidewalls. Further, in certain semiconductor devices having a plurality of like device features it is preferred that each of the device features meet certain size and shape constraints.
With this in mind, there are several problems with the device features
14
a
,
14
b
,
14
c
, and
14
d
, as depicted in FIG.
3
. These problems will be pointed out by referring to device features
14
b
and
14
c
. As shown, device features
14
b
and
14
c
do not have substantially vertical sidewalls, with respect to top surface
13
. In particular, device feature
14
b
has sloping sidewalls
24
a
on opposing sides, and device feature
14
c
has a sloping sidewall
24
a
adjacent to device feature
14
b
and a sloping sidewall
24
b
adjacent to design feature
14
d
. Notice that the angle, with respect to top surface
13
, of sloping sidewalls
24
a
is different than the angle, with respect to top surface
13
, of sloping sidewalls
24
b
. Consequently, device feature
14
b
has a different shape and size than device feature
14
c.
The difference in shapes of device features
14
b
and
14
c
can be traced to the etching process, and more particularly to the resist mask
16
. Referring back to
FIG. 2
, a residue
22
tends to form when plasma
18
contacts resist mask
16
during the etching process. As shown, residue
22
can build up within the etched openings
20
a-c
, and on the sidewalls of the design features. Residue
22
, which typically includes harder to etch polymers, tends to reduce the etching capability of plasma
18
to feature layer
14
. As a result, the sidewalls of the various device features tends to be non-vertical and in certain cases non-planar, as well.
The final shape of a given sidewall depends on several factors, including the amount of residue
22
that actually forms. The amount of residue
22
that forms appears to depend, at least partially, on the window
17
a-c
(e.g., shape, size, width, thickness, etc.) formed by resist mask
16
. For example, since window
17
c
is wider than windows
17
a
and
17
b
there tends to be more residue
22
build-up within etched opening
20
c
, which is formed through window
17
c
. Consequently, device features
14
b
and
14
c
are shaped differently and may perform differently.
Thus, there is a need for methods that provide increased process control during the formation of device features by reducing the deleterious effects of residue build-up.
SUMMARY OF THE INVENTION
The present invention provides methods that provide increased process control during the formation of device features. In accordance with certain aspects of the present invention, the amount of residue build-up is significantly reduced, if not substantially eliminated, by altering the resist mask prior to patterning the underlying layer and/or layers to form a device feature.
Thus, in accordance with certain embodiments of the present invention, a method for fabricating a device feature in a semiconductor device is provided. The method includes forming a second layer on a first layer and forming a resist mask on the second layer, wherein the resist mask has at least one opening that exposes a selected portion of a top surface of the underlying second layer. The method further includes raising the temperature of at least a portion of the resist mask sufficient to form a hard resist layer within the resist mask sufficient, and then etching through the selected portion of the second layer to expose a portion of the first layer. In accordance with certain preferred embodiments of the present invention, the step of raising the temperature of at least a portion of the resist mask further includes placing the semiconductor device in a chamber having an initial temperature that is less than about 150° C., and raising the temperature in the chamber from the initial temperature to a second temperature that is at least about 150° C. for a defined period of time. By way of example, in accordance with certain embodiments if the present invention, the second temperature is between about 150° C. and about 450° C., and/or the defined period of time is less than about 60 seconds.
The above stated needs and others are also met by a method for forming a hardened resist layer within a resist mask using rapid thermal anneal techniques, in accordance with still further embodiments of the present invention. The method includes forming a resist mask on a top layer of a layer stack, wherein the resist mask comprises a plurality of polymer molecules, and thermally heating at least a portion of the plurality of polymer molecules in the resist mask sufficient to form a hardened resist layer with cross-linked chains of polymer molecules in the resist mask. In accordance with certain embodiments of the present invention, the step of heating at least a
Shen Lewis
Yang Wenge
Advanced Micro Devices , Inc.
Perez-Ramos Vanessa
Utech Benjamin L.
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