RSSE optimization using hardware acceleration

Pulse or digital communications – Receivers – Particular pulse demodulator or detector

Reexamination Certificate

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Details

C375S262000

Reexamination Certificate

active

07372922

ABSTRACT:
A Reduced State Sequence Equalizer (RSSE) is implemented using a butterfly hardware accelerator (58) in the form of a butterfly to increase the efficiency of computing branch metrics (24) and the ACS (add, compare and select) function (26). Multiple path metrics between a first state and a second state may be computed responsive to the received symbols and reference constellation symbols and determining a best scenario at the second state using said butterfly circuitry. The received symbols may be rotated by a predetermined angle for computation of all minimums of two cosets in an 8-PSK constellation.

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