Row selector occupying a reduced device area for...

Details Row selector occupying a reduced device area for... Row selector occupying a reduced device area for...

2011-06-21

2011-06-21

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185110, C365S185330

Reexamination Certificate

active

07965561

ABSTRACT:
A memory device having a plurality of memory cells grouped in at least two memory sectors is disclosed. A first decoding circuit operable to receive address codes of the plurality of memory cells and to generate a plurality of decoding and selecting signals in response to the address codes. A plurality of second decoding circuits are coupled to the first decoding circuit and operable to generate driving signals for the memory cell address signal lines based at least in part on the plurality of decoding and selecting signals. A voltage shifting circuit is operable to generate a shift in the voltage of the plurality of decoding and selecting signals for generating a plurality of shifted voltage decoding and selecting signals and to provide the shifted decoding and selecting signals to the plurality of second decoding signals for generating the drive signals.

REFERENCES:
patent: 6115289 (2000-09-01), Sin
patent: 6434052 (2002-08-01), Son et al.
patent: 7468916 (2008-12-01), Chen
patent: 2009/0213669 (2009-08-01), Lee

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