Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-08-05
2001-07-10
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185330
Reexamination Certificate
active
06259631
ABSTRACT:
FIELD OF THE INVENTION
This invention broadly relates to drive circuits for semiconductor memories and more particularly concerns a row drive circuit for low voltage Flash EEPROM memories.
BACKGROUND
As it is known, in implementing memory circuits, particularly Flash EEPROM memories, a problem is raised in connection with the simultaneous existence within the circuit of logic signals as well as of signals variable within an extended voltage range and consequently with the need of simultaneous management of them. Such variable signals within an extended voltage range are intended to be used in the various operation modes of the memory, such as the read or programming or erasure operations. The logic signals, on the other hand, are control signals and are variable between ground voltage, as indicated by GND, and the supply voltage, as indicated by VDD. The normal supply voltage in these circuits, which are also designated as low voltage or low power circuits, is presently of about 3.3 volts, while the voltage used for performing operations such as internal programming or erasure operations can also reach 12 volts (for instance, 5 volts for read operations).
On the one side, this entails the need to implement various circuits on the chip to generate such higher voltages starting from the low supply voltage of 3.3 volts, and, on the other side, this entails the need to implement suitable circuits within the memory itself adapted to handle or manage these voltages higher than the supply voltage, without introducing time delays incompatible with a proper operation of the memory and consequently without affecting its access times. The essential requirement of these circuits, therefore, is related to their operation speed: these circuits are defined as voltage translators.
SUMMARY OF THE INVENTION
This invention is not aimed at generating such operation voltages higher than the supply voltage, but it is an object thereof to handle these voltages in very fast manner, while also a space saving is achieved on the silicon area.
More precisely, it is an object of this invention to provide a voltage translator circuit which, even if logic signals in a voltage range of 0 to 3.3 volts are applied to its input port and even if voltages in the range of −9 to 12 volts as generated by other suitable circuits are available thereto, is adapted to furnish output voltages fully variable within the latter range and also adapted to operate in very fast manner; in the same time such circuit ought to need a small silicon area for implementation.
Since the read time of a memory is a substantial feature thereof and since all read operations require a voltage higher than the supply voltage, the main but, of course, not exclusive application of this invention is to be identified in a row drive circuit for Flash EEPROM memories, by operating as a voltage translator circuit designed to couple such above mentioned read voltages to selected rows or wordlines of the memory.
Summarising all above said, in present Flash EEPROM memory technology with a supply voltage of 3.3 volts, the read operation are carried out by driving the selected wordline to 5 volts and all not-selected wordlines to ground GND. When other operations are to be carried out, such as programming or erasure operations, the concerned wordlines should be driven to other voltages, typically in the range −9 volts to 12 volts. High voltage transistors should be used, therefore, in said row drive circuits, in order to accommodate these voltages noticeably higher than the supply voltage. In P-channel or N-channel MOS transistor technology, said high voltage transistors offer rather poor performances with respect to low voltage transistors, as it is well known to those skilled in the art, due to the noticeable thickness of the required gate oxide. This is really the core of the problem, since in very fast applications, such as the above mentioned memories, with an access time in the range of 10 to 20 nsec, the row drive circuit should drive the selected wordlines in a very fast manner, even if high voltage transistor are employed, due to the fact that any delay in coupling the wordline driving voltages directly and adversely affects the memory access time.
Starting, therefore, from a situation entailing a Flash EEPROM memory having logic control voltages in the range of 0 to 3.3 volts as well as operation voltages (VX) for effecting read, programming or erasure operations in the range of −9 to 12 volts and comprising a decode section schematically represented as a NOR gate circuit which receives the selection signals coupled to an input node to an inverter circuit, it is specific subject-matter of this invention to provide a voltage translator circuit to drive the rows or wordlines of a memory, wherein:
the wordline to be driven is connected to ground through a first N-MOS type switch transistor, the gate of which is driven by the selection logic signal applied through said NOR gate circuit and said inverter circuit and it is connected to the operation voltage through a second P-MOS type switch transistor,
a first P-MOS type feedback transistor, the gate of which is directly driven by said wordline, is inserted between the operation voltage and the gate region of said second switch transistor,
a second N-MOS type feedback transistor, the gate of which is directly driven by said wordline, is inserted between the connection node of said first feedback transistor with the gate region of said second switch transistor and the input node on the gate region of said first switch transistor.
In the preferred embodiment, the connection node between said first feedback transistor and the gate region of said second switch transistor is connected to ground through a decoupling transistor of N-MOS type, the gate of which is driven by the selection signal once inverted and coming from the connection node between said NOR gate circuit and said inverter circuit.
REFERENCES:
patent: 4956816 (1990-09-01), Atsumi et al.
patent: 4999813 (1991-03-01), Ohtsuka et al.
patent: 5455789 (1995-10-01), Nakamura et al.
patent: 0356650 A2 (1990-03-01), None
Menichelli Stefano
Vali Tommaso
Petersen Bret J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tran Andrew Q.
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