Row decoding circuit for semiconductor non-volatile electrically

Details Row decoding circuit for semiconductor non-volatile electrically Row decoding circuit for semiconductor non-volatile electrically

1997-03-27

1998-12-08

Nelms, David

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518523, 36518511, 36518529, 326107, G11C 800

Patent

active

058480137

ABSTRACT:
The invention relates to a row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of the type which includes a matrix of memory cells laid out as cell rows and columns and is divided into sectors, said circuit being input row decode signals and supply voltages in order to drive an output stage incorporating a complementary pair of high-voltage MOS transistors of the pull-up and pull-down type, respectively, which are connected to form an output terminal connected to the rows of one sector of the matrix, characterized in that a MOS transistor of the P-channel depletion type with enhanced gate oxide is provided between the output terminal and the pull-down transistor. The control terminal of the depletion transistor forms a further input of the circuit.

REFERENCES:
patent: 5371705 (1994-12-01), Nakayama et al.
patent: 5463583 (1995-10-01), Takashina
patent: 5619450 (1997-04-01), Takeguchi
European Search Report from European Patent Application 96830174.7, filed Mar. 29, 1996.
IEICE Transactions On Electronics, vol. E77-c, No. 5, Mar. 1994, Tokyo JP, pp. 791-798, Atsumi, et al. "A 16 MB Flash EEPROM With A New Self Data Refresh Scheme For A Sector Erase Operation".

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