Row decoder with low gate induce drain leakage current

Details Row decoder with low gate induce drain leakage current Row decoder with low gate induce drain leakage current

2006-12-19

2006-12-19

Mai, Son L. (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189090, C365S230080

Reexamination Certificate

active

07151712

ABSTRACT:
A row decoder with low gate induce drain leakage current (GIDL) comprising a CMOS circuit is provided. The CMOS circuit comprises a first NMOS transistor and a first PMOS transistor. The row decoder of the present invention further comprises a second PMOS transistor and a local voltage generator. Wherein, a first source/drain of the second PMOS transistor is electrically coupled to a base of the first PMOS transistor, and a second source/drain of the second PMOS transistor is electrically coupled to a base thereof and a DC bias. Moreover, the local voltage generator provides a voltage signal to a gate of the second PMOS transistor, which controls the second PMOS transistor to work in conductive, partial conductive or open circuit mode.

REFERENCES:
patent: 5265052 (1993-11-01), D'Arrigo et al.
patent: 5703825 (1997-12-01), Akiba et al.
patent: 5870348 (1999-02-01), Tomishima et al.
patent: 6512705 (2003-01-01), Koelling et al.
patent: 6795348 (2004-09-01), Mihnea et al.

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