Row decoder having triple transistor word line drivers

Details Row decoder having triple transistor word line drivers Row decoder having triple transistor word line drivers

1996-04-18

1998-02-17

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518911, 326106, G11C 800

Patent

active

057198187

ABSTRACT:
A row decoder with a novel word-line driver is described. Each driver includes a p-channel select transistor and first and second, significantly separated, n-channel discharging transistors, all of whose drains are connected to the word-line to be controlled. The two discharging transistors are connected in different sections, such as on opposite sides, of the word-line. The driver is controlled by a control line, a select line and a disable line. When the control line is active, it enables the select transistor to select the word-line only if the select line is active. The discharging transistors are controlled through the disable line, discharging the word-lines when the disable line is strobed. In a second embodiment, the disabling activity is segmented such that only one block of the array is discharged at a time. A third embodiment shows the segmentation within an alternate metal, virtual ground array architecture.

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