Row decoder for semiconductor memory device

Details Row decoder for semiconductor memory device Row decoder for semiconductor memory device

1997-10-23

1999-09-07

Hoang, Huan

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523008, 365203, G11C 800

Patent

active

059497351

ABSTRACT:
The row decoder includes an internal node and an output node. A decoding unit receives a plurality of externally-applied address signals and pulls down the internal node to a logic low voltage when the plurality of address signals have an active state. A latch unit pulls up the output node to a logic high voltage in response to the pulling-down of the internal node by the decoding unit, pulls down the output node to the logic low voltage when the internal node is at the logic high voltage, and reduces a voltage at the internal node to a voltage less than the logic high voltage and greater than the logic low voltage based on a selection signal.

REFERENCES:
patent: 5351217 (1994-09-01), Jeon
patent: 5412331 (1995-05-01), Jun et al.
patent: 5615164 (1997-03-01), Kirihata et al.

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