Row decoder for driving word line at a plurality of points there

Details Row decoder for driving word line at a plurality of points there Row decoder for driving word line at a plurality of points there

1993-04-08

1995-02-28

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523001, 36523003, 307412, 326106, G11C 800

Patent

active

053943759

ABSTRACT:
A row decoder for a semiconductor memory device is disclosed which includes a plurality of decoding circuits each driving a corresponding one of word lines in response to first and second control signals associated therewith. Each of the decoding circuits includes a first node supplied with the first control signal, a second node supplied with the second control signal, a first transistor connected between the first node and the corresponding word line and turned ON when the second control signal takes an active level, and a second transistor connected between the corresponding word line and a reference potential terminal and turned ON when the second control signal takes an inactive level.

REFERENCES:
patent: 4429374 (1984-01-01), Tanimura
patent: 4697252 (1987-09-01), Furuyama et al.
patent: 4777390 (1988-10-01), Hoshi
patent: 5077495 (1991-12-01), Torimaru et al.
patent: 5252863 (1993-10-01), Hatsuda et al.
IEEE Joural of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1176-1183, Chou et al, "A 60 NS 16 Mbit DRAM with Minimized Sensing Delay Caused by Bit Line Stray Capacitance".
IEEE Transactions on Computer Aided Design of Integrated Circiuts and Systems, vol. 9, No. 3, Mar. 1990, pp. 236-247, Hoppe et al., "Optimization of High Speed CMOS Logic Circuits with Analytical Models for Signal Delay, Chip Area, and Dynamic Power Dissipation".

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