Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-06-16
2002-03-12
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185290, C365S230060
Reexamination Certificate
active
06356481
ABSTRACT:
TECHNICAL FIELD
The present invention regards a row decoder for a nonvolatile memory with possibility of selectively biasing the word lines with positive or negative voltages.
BACKGROUND OF THE INVENTION
As is known, nonvolatile memories comprise an array of cells arranged on rows and columns wherein word lines connect the gate terminals of the cells arranged on a same row, and bit lines connect the drain terminals of the cells arranged on a same column. Individual rows of the memory array are then addressed by a row decoder receiving at the input a coded address.
It is further known that, in a nonvolatile memory cell of the floating gate type, storage of a logic state is carried out by programming the threshold voltage of the memory cell so as to define the amount of electric charge stored in the floating gate region.
According to the stored information, memory cells may be distinguished into erased memory cells (stored logic state “1”), wherein no electric charge is stored in the floating gate region, and written or programmed memory cells (stored logic state “0”), wherein the electric charge stored in the floating gate region is sufficient to determine a sensible increase in the threshold voltage of the memory cells.
Erasing a nonvolatile memory is a highly complex operation, in that it entails a number of settings to be performed prior to proper erasing, when the electric charges present in the floating gate region is extracted and as a result the threshold voltage of the memory cells is reduced, and then entails verify operations and possibly further modifications after erasing when the result of erasing is not fully satisfactory.
In particular, to erase a sector, first of all a pre-conditioning operation is carried out, i.e., all the memory cells are brought to the programmed state regardless of their current state. Indeed, if a sector were erased wherein some of the memory cells are written but others have already been erased, during erasing there would be an over-erasing of the memory cells that have already been erased, so that these memory cells are very likely to become depleted, i.e., they have negative threshold voltage, and hence drain current even when their gate terminals are grounded. This effect proves particularly troublesome in that it simulates the constant presence of erased memory cells in the columns to which they belong, and thus all the memory cells belonging to these columns are read as being erased irrespective of their actual state.
In order to prevent this phenomenon and to render the history of all the memory cells belonging to the same sector uniform, writing of the entire sector is carried out.
Following upon the operation of pre-conditioning, all the memory cells of the sector are thus programmed and have threshold voltages with the distribution illustrated in FIG.
1
and identified with the binary information “0” associated to this distribution. For this distribution,
FIG. 1
also shows the typical minimum values for the threshold voltages.
Next proper erasing is carried out. In this phase, for a so called “negative gate” erasing, the drain and source terminals of the memory cells are appropriately biased in a per se known manner, and hence not described in detail, and an erase pulse typically having a duration of the order of 10 msec is applied on the gate terminals. Upon termination of the erase pulse, a verify operation is carried out on all the memory cells of the sector to check the value of their threshold voltages, and this verify operation is carried out by performing a marginal reading that will guarantee proper recognition of the memory cell in the normal read modality.
For this reason, erasing proceeds with applying an erase pulse followed by a verify operation until all the memory cells present a threshold voltage lower than a reference threshold voltage, the latter being the threshold voltage of the reference memory cell used during the verify operation.
At this point, all the memory cells of the sector have threshold voltages presenting the distribution illustrated in FIG.
1
and identified by the binary information “1” associated thereto, i.e., a distribution having a basically Gaussian form, in which the threshold voltage used during the verify operations referred to above is indicated by EV and is typically 2.5 V.
As may be noted from an analysis of
FIG. 1
, the distribution of the threshold voltages that is obtained after erasing has a form given by the superposition of a Gaussian curve and a tail due to the depleted memory cells.
Sector erasing cannot, however, be considered as yet concluded, because it is still necessary to ascertain whether there are depleted memory cells that may induce errors during reading.
Consequently, proper erasing is followed by a search phase for depleted memory cells, known as “soft-programming”, including verifying the presence of a leakage current on the columns of the memory array, with all the rows of the array kept grounded.
When a column that presents this fault is identified, the first memory cell of the column is addressed, and a programming pulse having a preset amplitude is applied to the gate terminal to slightly shift the threshold of the memory cell, without, however, exceeding the EV value mentioned above. Next, reading of the second memory cell in the same column is carried out. If the memory cell has no leakage current, this means that the depleted memory cell was the previous one which has already been recovered; otherwise, programming of the memory cell in question is carried out, and so forth until the end of the column is reached.
Once the end of the column has been reached, verify is then repeated and, if there is still a leakage current present, the above described procedure is repeated, this time, however, increasing the amplitude of the programming pulse applied to the gate terminal of the memory cells during programming.
As may be noted from the above description, searching for depleted memory cells is particularly laborious and requires not only a non-negligible execution time, but also the supply of a considerable current when programming the depleted memory cells.
This latter aspect is of particular importance in memory devices with single supply voltage. In this case, in fact, all the necessary high voltages are obtained from the single supply voltage available through charge pumps, which present, however, a very limited current capacity, typically of just a few mA, and thus allowing only a small number of columns containing depleted memory cells to be simultaneously recovered.
A further drawback involved in the procedure of searching for depleted memory cells as described above is due to the fact that the illustrated problems, which are linked to the presence of a depleted memory cell in one column (simulation of the presence of an entirely erased column when in actual fact there are still memory cells having threshold voltages higher than EV) becomes particularly important and may even lead to jeopardizing the functioning of the memory in case of multilevel memory cells, i.e., memory cells that are each able to store more than one bit.
In fact, considering for example memory cells each containing two bits, the number of distributions of the threshold voltages is four, one for each combination of the logic levels of the pair of bits stored in a cell, instead of two as in case of conventional memory cells storing a single bit.
FIG. 2
illustrates the distributions of the threshold voltages deriving from the use of four level memory cells, i.e., cells storing two bits. For each distribution, the maximum and minimum values typical of the threshold voltages and the binary information associated thereto are indicated.
As may be noted from a comparison between FIG.
2
and
FIG. 1
, the latter regarding distributions resulting from the use of conventional two level memory cells, i.e., ones storing a single bit, the four distributions resulting from the use of multilevel memory cells fall within the same range of threshold voltage values in which the two distributions
Campardo Giovanni
Carrera Marcello
Micheloni Rino
Ohba Atsushi
Carlson David V.
Jorgenson Lisa K.
Mai Son
SEED IP Law Group PLLC
STMicroelectronics S.r.l.
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