Row decoder for a memory device

Details Row decoder for a memory device Row decoder for a memory device

2008-12-30

2010-11-02

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230010, C365S230080

Reexamination Certificate

active

07826302

ABSTRACT:
A semiconductor memory device including an array of memory cells arranged in a plurality of rows and in a plurality of columns. The memory device further includes a plurality of word lines each associated with a respective row of the array and identified by a respective row address, and a row decoder configured to receive a current row address and select a word line according to said current row address. The row decoder includes a plurality of row selection units each associated with a respective word line and configured to receive the current row address; each row selection unit is configured to be enabled for biasing the respective word line to a selection voltage if the current row address identifies said word line. Each row selection unit includes a corresponding enabling device for enabling the row selection unit after a predetermined time from the reception of the current row address.

REFERENCES:
patent: 7606102 (2009-10-01), Blodgett
patent: 7660183 (2010-02-01), Ware et al.
patent: 2001/0033195 (2001-10-01), Kanda et al.
patent: 2008/0140974 (2008-06-01), Ware et al.

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