Row decoder circuit for use in non-volatile memory device

Details Row decoder circuit for use in non-volatile memory device Row decoder circuit for use in non-volatile memory device

2007-10-23

2007-10-23

Pham, Ly Duy (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S072000, C365S230060

Reexamination Certificate

active

11167984

ABSTRACT:
The invention disclosed herein is a non-volatile memory device. The non-volatile memory device comprises: a first transistor connected between a first voltage and a control node, and controlled by a second voltage; a second transistor connected between the first voltage and the control node, and controlled by a third voltage, and a word line driver for driving a word line in responsive to a voltage of the control node. The second voltage is set to a ground voltage during an erase operation. The third voltage is set to a power voltage during the erase operation.

REFERENCES:
patent: 5991198 (1999-11-01), Song et al.
patent: 6088267 (2000-07-01), Atsumi et al.
patent: 2001/0053093 (2001-12-01), Ogura et al.
patent: 2001/0053094 (2001-12-01), Otsuka
patent: 2002/0172088 (2002-11-01), Iorio et al.
patent: 2000-0027296 (2000-05-01), None
patent: 2000-0039095 (2002-05-01), None
patent: 2004-0008516 (2004-01-01), None
patent: 2004-0015901 (2004-02-01), None
English language abstract of Korean Publication No. 2000-0027296.
English language abstract of Korean Publication No. 2002-0039095.
English language abstract of Korean Publication No. 2004-0008516.
English language abstract of Korean Publication No. 2004-0015901.

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