Row decoder circuit for PMOS non-volatile memory cell which uses

Details Row decoder circuit for PMOS non-volatile memory cell which uses Row decoder circuit for PMOS non-volatile memory cell which uses

1997-02-22

1998-08-18

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518518, 36523006, G11C 1134

Patent

active

057966567

ABSTRACT:
A row decoder circuit selectively provides suitable programming, reading, and erasing voltages to an associated memory array employing PMOS floating gate transistors as memory cells. In some embodiments, during programming, the row decoder circuit pulls a selected word line of the associated memory array high to a programming voltage on a first voltage line and maintains an un-selected word line at a predetermined potential. During reading, the row decoder circuit discharges the word line, if selected, to ground potential, and maintains the word line, if un-selected, at a predetermined potential. During erasing, the row decoder circuit charges the word line to a high negative voltage. The row decoder circuit includes isolation means to electrically isolate the word line of the associated memory array from undesirable potentials during programming, reading, and erasing operations.

REFERENCES:
patent: 4977543 (1990-12-01), Kouzi
patent: 5265052 (1993-11-01), D'Arrigo et al.
patent: 5365479 (1994-11-01), Hoang et al.
patent: 5513146 (1996-04-01), Atsumi et al.
patent: 5513147 (1996-04-01), Prickett, Jr.

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