Row decoder circuit for an electronic memory device, particularl

Details Row decoder circuit for an electronic memory device, particularl Row decoder circuit for an electronic memory device, particularl

1998-12-29

2000-05-30

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518911, G11C 800

Patent

active

060698373

ABSTRACT:
A row decoding circuit for an electronic memory cell device, particularly in low supply voltage applications, is described. The row decoding circuit is adapted to boost, through at least one boost capacitor, a read voltage to be applied to a memory column containing a memory cell to be read. The circuit is powered between a first supply voltage reference and a second ground potential reference, and comprises a hierarchic structure of cascade connected inverters and a circuit means of progressively raising the read voltage level dynamically. First means are provided for raising the read voltage level to a value equal to the supply voltage plus a threshold voltage, and second means are provided for raising the read voltage level to a value equal to the supply voltage plus twice said threshold voltage.

REFERENCES:
patent: 4807190 (1989-02-01), Ishii et al.
patent: 5010259 (1991-04-01), Inoue et al.
patent: 5555216 (1996-09-01), Drouot
patent: 5602796 (1997-02-01), Sugio
patent: 5673225 (1997-09-01), Jeong et al.

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