Row decoder

Details Row decoder Row decoder

1997-11-19

2000-04-25

Phan, Trong

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365203, 365204, G11C 800, G11C 700

Patent

active

060552034

ABSTRACT:
A row decoder for controlling a plurality of selectable word-lines has one control line per block of N word-lines, K select lines, at least one disable line and one word-line driver per word-line. Each control line is activatable during a charge period and during an initial portion of a discharge period. Each select line is selectably high during the charge period. The disable line is active during the discharge period. Each driver includes an access transistor and a discharge transistor. The access transistor is located at one end of its word-line and the discharge transistor is connected at the other end. The access transistor is controlled by one control line and is connected between one select line and the word-line. The discharge transistor is controlled by one disable signal and is connected between the word-line and a ground supply.

REFERENCES:
patent: 4259731 (1981-03-01), Moench
patent: 4360902 (1982-11-01), Proebsting
patent: 4401903 (1983-08-01), Iizuka
patent: 4724341 (1988-02-01), Yamada et al.
patent: 4788457 (1988-11-01), Mashiko et al.
patent: 4798977 (1989-01-01), Sakui et al.
patent: 4843261 (1989-06-01), Chappell et al.
patent: 5018107 (1991-05-01), Yoshida
patent: 5282175 (1994-01-01), Fujita et al.
patent: 5416741 (1995-05-01), Ohsawa
patent: 5446859 (1995-08-01), Shin et al.
patent: 5519665 (1996-05-01), Chishiki
patent: 5528540 (1996-06-01), Shibata et al.
patent: 5602796 (1997-02-01), Sugio
patent: 5610872 (1997-03-01), Toda
patent: 5612924 (1997-03-01), Miyamoto
patent: 5633832 (1997-05-01), Patel et al.
patent: 5640359 (1997-06-01), Suzuki et al.
patent: 5761135 (1998-06-01), Lee
S.B. Ali et al., "A50-ns 256K CMOS Split-Gate EPROM", IEEE Journal of Solid State Circuits, vol. 23, No. 1, pp. 79-85, Feb. 1988.
Katsuyuki Sato et al., "a-4Mb Pseudo SRAM Operating at 2.6 .+-. IV with 3-.mu.A Data Retention Current", IEEE Journal of Solid-State Circuits, vol. 26, No. 11, pp. 1556-1562, Nov. 1991.
R. Shirota et al., "An Accurate Model of Subbreakdown Due to Band-To-Band Tunneling and its Application", IEDM Technical Digest, pp. 26-27, Dec. 1988.
Tomohisa Wada et al., "Simple Noise Model and Low-Noise Data-Output Buffer for Ultrahigh-Speed Memories", IEEE Journal of Solid-State Circuits, vol. 25, No. 6, pp. 1586-1588, Dec. 1990.
Manabu Ando et al., "A 0.1-.mu.A Standby Current, Ground-Bounce-Immune 1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits, vol. 24, No. 6, pp. 1708-1710, Dec. 1989.
Douseki et al., "Fast-Access BiCMOS SRAM Architecture with a V.sub.ss Generator" IEEE Journal of Solid-State Circuits, vol. 26, No. 4, pp. 513-517, Apr. 1991.

Affiliated with

Also associated with

Rating

Row decoder does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Row decoder, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Row decoder will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-999052