Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-05-08
2001-08-14
Shankar, Vijay (Department: 2778)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
Reexamination Certificate
active
06275202
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the field of electronic circuitry, and more particularly to address decoders such as are used for decoding row or column information in a video display device. The predominant current usage of the inventive optimized row decoder is in the decoding of row information in video display devices wherein the ability to rapidly change states is important.
BACKGROUND ART
Row and column decoders are well known in the art for activating rows and columns in array devices. Many array devices are memory arrays, and the technology of row decoders has, in great part, been developed for use with such memory devices. Another type of array device is the array display device. This category includes liquid crystal display (“LCD”) devices. In general, a row decoder is used to activate a particular row of the display such that data present on a plurality of column lines will affect the intended row. To date, the row and column decoders used with such video display devices are not substantially different in concept from comparable devices which are used in conjunction with memory array devices.
Another device known in the field is the predecoder. One skilled in the art will recognize that a predecoder will allow a required amount of binary data to be transmitted on fewer data lines than might be required if the data were not to be “predecoded”. For example, four different row addresses can be referenced according to the four different logical state combinations of two data lines.
It is known in the art that capacitive interaction between adjoining data lines will substantially detract from the ability of such lines to change state rapidly. Where one line of two adjacent lines is changing state, this is somewhat of a problem. However, where the two adjacent lines are simultaneously attempting to change states in opposite direction (one is going high, while the other is going low), this problem is severely compounded, especially when the adjacent lines are long.
It would be a significant improvement if a method or apparatus were found to decrease the detrimental effect caused by the simultaneous state changes of adjacent data lines within a row or column decoder. This is particularly important given the present quest for increased speed and/or lower power consumption. (In this case, as in many such instances, there is a trade off between speed and power consumption. That is, a decrease in the capacitive interaction between adjacent lines could be used to cause greater operational speed for a given applied power. Alternatively, less power could be used to achieve the same speed, or some combination of improved speed and power consumption could be accomplished.) However, to the inventor's knowledge, no such improvement in the design of row and column decoders has been presented prior to the present invention.
DISCLOSURE OF INVENTION
Accordingly, it is an object of the present invention to provide a row and/or column decoder which will change states faster than comparable prior art decoders.
It is still another object of the present invention to provide a row and/or column decoder which can achieve a desired speed using less power than prior art devices.
It is yet another object of the present invention to provide a method and apparatus for reducing the effect of sideways capacitive coupling in adjacent data lines in particular applications.
It is still another object of the present invention to provide a method and apparatus for improving the performance of row and/or column decoders which does not effectively increase the cost of producing the decoders.
It is yet another object of the present invention to provide a method and apparatus for improving the performance of row and/or column decoders which does not take up a great deal of real estate on an integrated circuit.
Briefly, an embodiment of the present invention is an improved row decoder for a video display device which has row addressing lines configured such that no two adjacent lines will be switching states simultaneously. The invention takes advantage of the fact that the rows of the video display device, unlike rows or columns of memory array devices, will generally be switching sequentially. That is, the rows are addressed in order, for example beginning at the top of a screen and progressing in order to the bottom of the screen. This makes possible the inventive physical layout.
An advantage of the present invention is that video display devices can be caused to operate more quickly.
A further advantage of the present invention is that row and/or column decoders can be operated using less power.
Yet another advantage of the present invention is that it can be readily implemented into existing row and/or column decoder designs without extensive modification.
These and other objects and advantages of the present invention will become clear to those skilled in the art in view of the description of the described mode of carrying out the invention and the industrial applicability of the embodiment as described herein and as illustrated in the several figures of the drawing.
REFERENCES:
patent: 5652600 (1997-07-01), Khormaei et al.
patent: 5787097 (1998-07-01), Roohparvar
patent: 5801672 (1998-09-01), Masuda et al.
patent: 5844535 (1998-12-01), Itoh et al.
Date Book, vol. 2, Texas Instruments pp. 2-85 to 2-89, 1993.
Aurora Systems, Inc.
Henneman & Saunders
Henneman, Jr. Larry E.
Shankar Vijay
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