Row address generator for defective DRAMS including an upper and

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Details

395400, 3642431, 3642453, 3642464, G06F 1202

Patent

active

052533549

ABSTRACT:
A row address generator permits defective dynamic random access memory devices to be addressed by forcing the most-significant bit of the row address to a logical one if the upper half of the defective DRAM is operative and the lower half is inoperative and by forcing the most-significant bit of the row address to a logical zero if the lower half of the DRAM is operative and the upper half is inoperative. A configuration register provides a control signal indicative of the half of the defective DRAM which is operative and a memory access detector provides an access control signal when the defective DRAM device is addressed. A row address control forces the most-significant bit to the proper level responsive to the configuration register and the memory access detector.

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