Row address decoder and word line driver unit with pull-down tra

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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36518906, G11C 11407

Patent

active

052951162

ABSTRACT:
A row address decoder and word line driver unit selectively drives a word line selected from one of a plurality sets of word lines, and comprises a plurality of row address decoders and word line driver sub-units for selecting a set of word lines and a plurality of address decoder sub-units for selecting a word line from the selected set of word lines, wherein a pair of p-channel enhancement type transfer transistors coupled between a selected row address decoder and word line driver unit and the selected word line are switched by a selected address decoder sub-unit for supplying a word line driving signal, the complementary word line driving signal switches an n-channel enhancement type first pull-down transistor coupled between the selected word line and a ground voltage line, and the selected address decoder sub-unit further switches an n-channel enhancement type second pull-down transistor, thereby charging to and discharging from the selected word line through the transistors operable in the saturation region.

REFERENCES:
patent: 4811304 (1989-03-01), Matsuda et al.
patent: 5051959 (1991-09-01), Nakano ett al.
patent: 5214602 (1993-05-01), Lines

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