Row address decoder and semiconductor memory device having...

Details Row address decoder and semiconductor memory device having... Row address decoder and semiconductor memory device having...

2008-12-29

2011-12-06

Le, Vu (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S185120, C365S185130, C365S201000, C365S230010

Reexamination Certificate

active

08072835

ABSTRACT:
A row address decoder includes a first main word line decoding unit decoding first and second row addresses to generate first to fourth main decoding signals. When a data storage test is performed, the first to fourth main decoding signals are enabled at first to fourth timings, respectively. The row address decoder also includes a second main word line decoding unit decoding third and fourth row addresses to generate fifth to eighth main decoding signals. When a data storage test is performed, the fifth to eight main decoding signals are enabled at first to fourth timings, respectively. A main word line enable signal generating unit decodes the first to fourth main decoding signals and the fifth to eighth main decoding signals to generate first to sixteenth main word line enable signals that are enabled at different times.

REFERENCES:
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patent: 2008/0094890 (2008-04-01), Kim et al.
patent: 2009/0097344 (2009-04-01), Park
patent: 2010/0309739 (2010-12-01), An
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patent: 1020040054362 (2004-06-01), None
patent: 1020050098336 (2005-10-01), None

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