Row address controller

Details Row address controller Row address controller

2007-03-08

2008-12-16

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230030

Reexamination Certificate

active

07466621

ABSTRACT:
Disclosed is a row address controller comprising: a bank control unit generating an active pulse and a precharge pulse, a word line clear signal and a block selection enable signal using the active pulse and precharge pulse. An address decoder latches and decodes a row address signal in response to a decoder enable signal and outputs a first and second address signals. A block selection unit generates a block selection signal in response to a redundancy signal, a repair signal, the word line clear signal, the block selection signal and the first address signal. A block control unit generates a word line latch signal in response to the precharge pulse and block selection signal A latch unit latches and outputs the second address signal in response to the word line latch signal.

REFERENCES:
patent: 6269046 (2001-07-01), Lee et al.
patent: 6304989 (2001-10-01), Kraus et al.
patent: 7397715 (2008-07-01), Lim et al.
patent: 100192573 (1999-01-01), None
patent: 100224681 (1999-07-01), None
patent: 19990086099 (1999-12-01), None
patent: 1020010109572 (2001-12-01), None

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