Row access information transfer device using internal wiring...

Details Row access information transfer device using internal wiring... Row access information transfer device using internal wiring...

2002-05-22

2004-08-03

Auduong, Gene N. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060, C365S225700

Reexamination Certificate

active

06771555

ABSTRACT:

TECHNICAL FIELD
1. Field of the Invention
A dynamic random access memory (DRAM) device, and more particularly a row access information transfer device using internal wiring of a memory cell array to communicate instructions to a column fuse box array is disclosed.
2. Description of the Prior Art
FIG. 1
is a block diagram of a conventional row access information transfer device, which illustrates a hierarchical wordline mode. A row block decoder
60
and a column fuse box array
70
are positioned at an angle of 90 degrees. The row block decoder
60
produces a row block select signal and outputs to corresponding block control units (
0
to M) within a row block control unit
10
. Further, the row block decoder
60
serves to transfer a row block signal (accessed by a row address received from a row address predecoder
40
and a row redundancy signal from a row fuse
50
) to the column fuse box array
70
when DRAM is activated. A column decoder
30
selects a specific column using a column address signal and a column redundancy signal from the column fuse box array
70
.
The row address predecoder
40
decodes an inputted row address responsive to an active command from DRAM and outputs the decoded signal to a main wordline driver
11
and to the row block decoder
60
. At this time, the logic state of a row redundancy signal inputted from a row fuse
50
determines whether a wordline corresponding to the inputted row address is repaired or not. Also, each of the block control units (
0
to M) within the row control unit
10
activates a corresponding row block (
0
to M) in response to the row block select signal from the row block decoder
60
.
The block control units (
0
to M) outputs the block select signal (msb) for controlling a wordline and a sense amplifier to a corresponding row block depending on the row block select signal received from the row block decoder
60
.
According to, the conventional row access information transfer device, the row block decoder
60
transfers M row block signals to the column fuse box array
70
. Therefore, the row block decoder
60
again encodes a row address (which had been pre-decoded in the row address predecoder
40
) and the decoded row redundancy signal.
In DRAM, since a circuit corresponding to a row block decoder
60
, a circuit corresponding to a column decoder
30
and various supply lines co-exist at a region where the row decoder and the column decoder intersect each other, the circuit construction and the wiring are very complicated. Moreover, the conventional row access information transfer device is disadvantageous in that it requires M additional bus lines to transfer M row block signals from in the row block decoder
60
to the column fuse box array
70
. The efficiency of use area and wiring is degraded in the intersecting region of the row block decoder
60
and the column decoder
30
.
SUMMARY OF THE DISCLOSURE
A row access information transfer device is provided which includes a memory cell array; and a row control unit for decoding a row address signal and a row redundancy signal and for outputting a block select signal for selecting a corresponding row block and a row block signal. The device also includes a column fuse box array responsive to the row block signal. A path for transferring the row block signal from the row control unit to the column fuse box array is at lest partially within the memory cell array.


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