Roving range control to limit receive PLL frequency of operation

Oscillators – Automatic frequency stabilization using a phase or frequency... – Plural oscillators controlled

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331 11, 331 17, 331 23, 331DIG2, 327147, 375376, H03L 707, H03L 7087

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active

059528885

ABSTRACT:
A circuit comprising a plurality of phase locked loop circuits, a control circuit and a plurality of storage elements. Each of the plurality of phase locked loop circuits may present a recovered data signal and a recovered clock signal in response to one of a plurality of serial data streams, a clock signal and one of a plurality of indication signals. The control circuit may present a counter signal in response to the recovered clock signals. The plurality of storage elements may each be configured to present one of the indication signals in response to the clock signal, a select signal and the counter signal.

REFERENCES:
patent: 5015970 (1991-05-01), Williams et al.
patent: 5081705 (1992-01-01), Swanke
Cypress Data Communications Data Book, CY7B951 Local Area Network ATM Transceiver, 1996, pp. 3-1 to 3-8.
Cypress Data Communications Data Book, CY7B952 SONET/SDH Serial Transceiver, 1996, pp. 3-9 to 3-15.
Cypress Data Communications Data Book, CY7B923 CY7B933, Transmitter/Receiver, 1996, pp. 4-1 to 4-27.
Practical Data Communications by Roger L. Freeman, 1995, pp. 130 to 286; John Wiley & Sons, Inc.
Cypress CY7C955, AX.TM. ATM-SONET/SDH Transceiver, Jul. 1997, pp. 2 to 76.

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