Routing vias in a substrate from bypass capacitor pads

Details Routing vias in a substrate from bypass capacitor pads Routing vias in a substrate from bypass capacitor pads

2006-07-11

2006-07-11

Tran, Mai-Huong (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C361S302000, C361S306100, C257S532000

Reexamination Certificate

active

07075185

ABSTRACT:
A method for routing vias in a multilayer substrate from bypass capacitor pads is disclosed. One embodiment of a method may comprise arranging a bypass capacitor power pad spaced apart from a bypass capacitor ground pad on a first surface of the multilayer substrate, routing a plurality of power vias from the bypass capacitor power pad to a first redistribution layer spaced from the first surface, and routing a plurality of ground vias from the bypass capacitor ground pad to the first redistribution layer. The methodology may further comprise jogging the plurality of ground vias at the first redistribution layer to the plurality of power vias to provide a power and ground via pattern, and routing the power and ground vias from the first redistribution layer to a second redistribution layer spaced apart from the first redistribution layer based on the power and ground via pattern.

REFERENCES:
patent: 6344961 (2002-02-01), Naito et al.
patent: 6440770 (2002-08-01), Banerjee et al.
patent: 6620728 (2003-09-01), Lin
patent: 6707145 (2004-03-01), Pollock et al.

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