Routing technique for a hierarchical interprocessor-communicatio

Details Routing technique for a hierarchical interprocessor-communicatio Routing technique for a hierarchical interprocessor-communicatio

1991-05-09

1993-06-29

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 941, 34082502, H04J 324

Patent

active

052241009

ABSTRACT:
A routing process for a single-instruction-multiple-data (SIMD) multi-level hierarchical network of nodes, which are arranged in clusters and interconnected by dual, unidirectional channels, are used to send data packets including routing address information during a succession of routing cycles from transmitting ones to receiving ones of a large number of parallel processors (e.g., 4096 processors arranged in a hierarchy of 8 cabinets, each of which contains a cluster of 8 circuit boards, with each circuit board containing a cluster of 64 processors). Each of the nodes includes a storage buffer having a capacity equal to a given number which is one more than the total number of channels terminating at that node. This routing process guarantees prevention of deadlock between levels and buffer overflow, and offers high-speed, low-cost interprocessor communication for SIMD computers.

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