Boots – shoes – and leggings
Patent
1989-10-10
1991-12-10
Lall, Parshotam S.
Boots, shoes, and leggings
364490, 364489, 364488, G06F 1560
Patent
active
050724029
ABSTRACT:
A system and method for routing interconnections through the layout of an integrated circuit is used in conjunction with a sliceable circuit layout specification that specifies the regions of the layout occupied by circuit components, a specification of the locations of terminals in the layout, and a netlist specifying for each terminal the set of other terminals that are to be connected to it. The regions of the circuit layout not occupied by circuit components are called routing regions. The circuit layout is sequentially sliced, defining a series of rectangular channels, each of which divides a region of the circuit layout containing two or more circuit components into two circuit regions each having at least one circuit component. For each channel, if there are one or more neighboring indented routing regions, a special channel is defined for each such indentation. After the entire routing region is divided into channels and special channels, interconnections are routed through those channels and special channels. In particular, before routing interconnections through each channel, interconnections are routed through the corresponding special channels, if any. A data structure is defined for denoting the sequence in which the channels are defined, the region of the layout occupied by each channel, and for each channel, the region of said layout occupied by each corresponding special channel, if any. The order in which channels are routed corresponds to the sequence in which channels were defined, as denoted in the data structure.
REFERENCES:
patent: 4577276 (1986-03-01), Dunlop et al.
patent: 4613941 (1986-09-01), Smith et al.
patent: 4636965 (1987-01-01), Smith et al.
patent: 4910680 (1990-03-01), Hiwatashi
Wei-Ming Dai et al., "A New Routing Region Definition and Ordering Scheme Using L-Shaped Channels", IEEE Proceedings of ISCAS 85, pp. 29-30.
Chi-Ping Hsu, "A New Two-Dimensional Routing Algorithm", 19th Design Automation Conference, IEEE 1985, pp. 46-50.
T. Hiwatashi et al., "A Hierarchical Routing System for VLSIs Including Large Macros", IEEE 1986 Custom Integrated Circuits Conference, pp. 235-238.
J. Hudson et al., "Rectilinear Area Routing: A Channel Router Approach", IEEE 1985 CICC, pp. 468-471.
H. Sai et al., "An Automatic Routing System for General Cell VLSI Circuits", IEEE 1985 CICC, pp. 68-71.
H. Krohn, "An Over-Cell Gate Array Channel Router", IEEE 1983, 20th Design Automation Conference, pp. 665-670.
M. Terai et al., "A Routing Program Application to Various Chip Structures of Gate Arrays", Joho Shori Gakkai, Ronbunshi, vol. 25, No. 3, May 1984, pp. 357-364.
David Hsu et al., "The Chip Compiler, an Automated Standard Cell/Macrocell Physical Design Tool", IEEE 1987 CICC, pp. 488-491.
S. Kimura et al., "An Automatic Routing Scheme for General Cell LSI", IEEE Trans. on CAD, Oct. 1983, pp. 285-292.
Dai et al., "Routing Region Definition and Ordering Scheme for Building-Block Layout", IEEE Trans. CAD, vol. CAD-4, No. 3, Jul. 1985, pp. 189-197.
C. H. Ng, "A Gridless Variable-Width Channel Router for Macro Cell Design", Proc. 24th Design Automation Conf. 1987.
Ashtaputre Sunil V.
Mody Rajiv C.
Lall Parshotam S.
Trans V. N.
VLSI Technology Inc.
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