Routing signals to pins of components in programmable logic...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing

Reexamination Certificate

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Reexamination Certificate

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08069431

ABSTRACT:
Various techniques are provided for routing signals to pins of components of programmable logic devices (PLDs). In one example, a computer-implemented method of routing signals in a PLD includes routing a plurality of signals to pins of a component of the PLD. At least two of the signals are routed to a same pin. The method also includes, for each of the signals routed to the same pin, determining a cost value associated with each of two or more pins. the method also includes, for each of the signals routed to the same pin, rerouting the signal to one of the two or more pins having the lowest cost value. The method also includes repeating the determining a cost value and the rerouting until no more than one signal is routed to a pin.

REFERENCES:
patent: 6631510 (2003-10-01), Betz et al.
patent: 6877040 (2005-04-01), Nam et al.
patent: 7111268 (2006-09-01), Anderson et al.
patent: 7134112 (2006-11-01), Anderson et al.
patent: 7376926 (2008-05-01), Kong et al.
patent: 7424697 (2008-09-01), Arslan et al.
patent: 7735047 (2010-06-01), Anderson et al.
patent: 7814452 (2010-10-01), Jang et al.
patent: 2005/0156626 (2005-07-01), Tomar et al.
patent: 2007/0300193 (2007-12-01), Lillis et al.
patent: 2009/0249276 (2009-10-01), Wu et al.
patent: 2009/0300571 (2009-12-01), Wu et al.
Naveed A. Sherwani, Algorithms for VLSI Physical Design Automation, Third Edition, 1999, pp. 261-263.
Ebeling et al., Placement and Routing Tools for the Triptych FPGA, IEEE Transactions on VLSI Systems, vol. 3, No. 4, Dec. 1995, pp. 473-482.
McMurchie et al., PathFinder: A Negotiation-Based Peformance-Driven Router for FPGAs, Proceedings of Third International ACM/SIGDA Symposium on Field Programmable Gate Arrays, Feb. 1995, pp. 111-117.
Optimized FPGA Architecture for Low Cost Applications, http://www.latticesemi.com/products/fpga/ecp2/optimizedfpgaarchitecture.cfm, printed Nov. 25, 2008, 2 pages.
Brown et al., A Detailed Router for Field-Programmable Gate Arrays, IEEE Transactions on Computer-Aided Design, vol. 11, No. 5, May 1992, pp. 620-628.
Maze Router: Lee Algorithm, http://www.ece.northwestern.edu/˜haizhou/357/lec6.pdf, pp. 1-18, Before Mar. 18, 2009.

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