Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Patent
1992-05-18
1995-01-03
James, Andrew J.
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
257207, 257208, H01L 2348, H01L 2944, H01L 2952, H01L 2960
Patent
active
053789253
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
This invention relates generally to a layout arrangement of a microelectronic device in which a plurality of interconnect lines, such as signal wirings for driving a decoder circuit in a memory chip, are arranged in parallel with power supply lines, and more particularly relates to a semiconductor integrated circuit device using two or more layers of interconnect lines.
FIG. 4 shows a layout of a conventional memory chip. Memory chip 1 is a read-only memory (ROM), and is composed of four memory cell blocks 2a to 2d. Between memory cell blocks 2a and 2b are arranged a row decoder circuit 3a including a decoder and a buffer for driving a word line of memory cell block 2a and a row decoder circuit 3b of memory cell block 2b so as to confront each other. Between memory cell blocks 2c and 2d are also arranged respective row decoder circuits 3c and 3d so as to confront each other.
In an upper part of FIG. 4, column decoder circuits 5a to 5d and sense amplifier circuits 6a to 6d for processing signals of bit lines of respective memory cell blocks 2a to 2d are arranged for memory cell blocks 2a to 2d, respectively. In a lower part of FIG. 4, peripheral circuits 4a and 4b including predecoder circuits in which signals for driving the row decoders and so forth are arranged for memory cell blocks 2a to 2d as shown. Peripheral circuit 4a is a circuit common to decoder circuits 3a and 3b, and arranged under memory cell blocks 2a and 2b. Peripheral circuit 4b is a circuit common to decoder circuits 3c and 3d, and arranged under memory cell blocks 2c and 2d .
In the arrangement of power supply wirings for supplying power to these circuits, a pad 7 supplied with Vss (0V) is formed on the outer circumferential side of sense amplifier circuits 6a and 6b. A main wiring 11 is arranged around chip 1 from pad 7, and Vss is applied to respective circuits by branch wirings 12 which are arranged in parallel with respective circuits so as to run towards the center of chip 1 from mother wiring 11. In memory cell blocks 2a to 2d and row decoder circuits 3a to 3d, Vss is supplied to respective cells 2a to 2d and circuits 3a to 3d through branch wirings 13 branched further from a part 12a of branch wirings 12.
A pad 8 supplied with Vdd (5V) is formed on the outer circumferential side of predecoder circuits 4a and 4b. A main wiring 21 is formed from pad 8 in-between memory cell blocks 2b and 2c, and Vdd is supplied to respective circuits through branch wirings 22 arranged in parallel with respective circuits from mother wiring 21 toward the circumference of chip 1. In row decoder circuits 3a to 3d, Vdd is supplied to decoder circuits 3a to 3d through branch wirings 23 branched further from a part 22a of branch wiring 22.
As described above, the power supply lines, Vss and Vdd, are arranged in separated positions so that Vss is supplied from the outer circumference to the center of chip 1 and Vdd is supplied from the center to the outer circumference. By adopting such a layout that wiring channels of Vss and Vdd are separated, wirings of Vss and Vdd avoid intersecting each other.
In chip 1 having such a layout, a region II where signal wirings which connect peripheral circuits 4a and 4b and row decoders 3a to 3d with one another gather together is a region where signal wirings and power supply wirings intersect one another, and is also one of wiring channels having the highest density in chip 1. Thus, the layout of region II is one of the most important factors for determining access speed and chip size of memory chip 1.
FIG. 5 shows a layout of region II in a conventional device. In a common bus region 30 between row decoder circuits 3a and 3b, n lines of signal wirings 31.1 to 31.n from peripheral circuit 4a to decoder circuits 3a and 3b are arranged in parallel with one another while being placed between power supply wirings 23a and 23b. Wirings 31.1 to 31.n are connected with respective jumpers 42.1 to 42.n of n pieces of function cells 41.1 to 41.n of peripheral circuit 4a. The wirings for signals output
REFERENCES:
patent: 4748494 (1988-05-01), Yamada et al.
patent: 4914503 (1990-04-01), Shirato et al.
patent: 4989062 (1991-01-01), Takahashi et al.
patent: 5119169 (1992-06-01), Kozono et al.
Clark S. V.
James Andrew J.
Janofsky Eric B.
Seiko Epson Corporation
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