Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing
Reexamination Certificate
2005-07-14
2009-06-23
Dennison, J Bret (Department: 2443)
Electrical computers and digital processing systems: multicomput
Computer-to-computer data routing
C718S103000
Reexamination Certificate
active
07552236
ABSTRACT:
A method, apparatus, system, and signal-bearing medium that, in an embodiment, detect a new task priority for a processor, where the processor is connected to a first node, find a home node for the processor via a cluster to which the processor belongs, and send the new task priority to the home node if the home node is different from the first node. In another embodiment, an interrupt directed to a first processor is detected, the interrupt is determined to be redirectable, a home node for the first process is found via a cluster to which the first processor belongs, and an interrupt vector is sent to the home node if the home node is different from the first node.
REFERENCES:
patent: 6205508 (2001-03-01), Bailey et al.
patent: 6658485 (2003-12-01), Baber et al.
patent: 6684280 (2004-01-01), Chauvel et al.
patent: 6823512 (2004-11-01), Miller et al.
patent: 6928647 (2005-08-01), Sager
patent: 7207040 (2007-04-01), Boudnik et al.
patent: 2003/0061423 (2003-03-01), Rankin et al.
patent: 2004/0034856 (2004-02-01), Boudnik et al.
patent: 2007/0143514 (2007-06-01), Kaushik et al.
Greenfield Todd Alan
Kriegel Jon K.
Dennison J Bret
Gamon Owen J.
International Business Machines - Corporation
LandOfFree
Routing interrupts in a multi-node system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Routing interrupts in a multi-node system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Routing interrupts in a multi-node system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4146906