Routing design method and routing design apparatus

Details Routing design method and routing design apparatus Routing design method and routing design apparatus

1997-03-04

1999-07-20

Teska, Kevin J.

Boots, shoes, and leggings

G06F 1750

Patent

active

059263970

ABSTRACT:
A routing design method applied to an integrated circuit such as an LSI includes the steps of (1) placing a cell serving as a source of signals (source cell) and cells serving as destinations of the signals (destination cells), (2) providing a minimum number of relay spots required on paths between the source cell and the destination cells, (3) providing wires on the paths, (4) extracting parasitic components (wire capacitances and wire resistances) of the wires, and (5) determining delay adjusting elements (cells) to be inserted in the relay spots in accordance with the extracted parasitic components, so that each delay adjusting element has a minimum size. The delay adjusting elements thus determined are inserted in the relay spots.

REFERENCES:
patent: 5367469 (1994-11-01), Hartoog
patent: 5410491 (1995-04-01), Minami
patent: 5461576 (1995-10-01), Tsay et al.
patent: 5475607 (1995-12-01), Apte et al.
patent: 5564022 (1996-10-01), Debnath et al.
patent: 5638291 (1997-06-01), Li et al.
Cho et al. ("A buffer distribution algorithm for high-performance clock net optimization", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 3, No. 1, pp. 84-98, Mar. 1995).

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