Multiplex communications – Diagnostic testing – Fault detection
Reexamination Certificate
1998-06-25
2002-04-16
Kizou, Hassan (Department: 2662)
Multiplex communications
Diagnostic testing
Fault detection
C370S248000
Reexamination Certificate
active
06373819
ABSTRACT:
BACKGROUND
The present invention according to a first aspect relates to a terminal unit for a TS switch, said terminal unit comprising a terminal function forming a user part of the terminal unit, and a switch terminating unit forming a switch port, there being bidirectional transfer of signals, including parity supervised signals, between the terminal function and the switch terminating unit, said signals being organized in frames containing a number of time slots.
According to a second aspect the invention relates to a method and a system for detecting faults in fault detecting hardware designed to detect faults in a data flow.
U.S. Pat. No. 4,532,624 describes parity testing in a telecommunication system. Parity errors are collected in common and erroneous parity may be generated to the different parity circuits, one at a time, for deciding from where the parity error originated.
U.S. Pat. No. 4,485,467 describes a digital switch matrix with built-in diagnostic functions, comprising parity checking and verifying parity checking, the latter consisting in forcing a predetermined data with even parity to test the parity checking circuit.
U.S. Pat. No. 4,821,256 discloses priority testing of a switch network. When a parity error has been found in one transmission direction, the parity bit created for transmission in the other transmission direction is made erroneous. If the other side sets the parity bit to the wrong level, it is however not described how it would be possible to establish where in the near end the error is located.
U.S. Pat. No. 4,393,490 discloses fault identification in a TS switch for detecting bad parity. The switch has a redundancy structure consisting of two planes. An alternative pattern is made to replace a pattern with erroneous parity. The part terminating the two planes detects this alternative pattern and replaces it by data from the other plane.
In WO 83/04355 parity is used for supervising time slots. An established connection is checked by generating erroneous parity and detecting where they appear.
SUMMARY
In a system according to the first aspect of the invention as indicated by way of introduction, maintenance is important to enabling identification of the nature and location of faults. There is also a need of having overlapping supervision functions to be able to cover all faults. It is also desirable to make such functions autonomous in hardware with the analyzing part in software to avoid obtaining status “OK” due to a fault in the hardware.
It is an object of the invention to realize such an overlapping supervision in a terminal unit of the kind indicated.
According to the invention there is, in this terminal unit, a first parity fault generating means in the switch terminating unit for generating in a test time slot (MFPE), included in said number of time slots and intended for parity function routine tests, a parity fault in a determined one of the frames sent to the terminal function. This produces an expected number of faults in the frames sent to the terminal function. A second parity fault generating means in the terminal function generates a parity fault in the test time slot in a determined one of the frames sent to the switch terminating unit. This produces an expected number of faults in the frames sent to the switch terminating unit. The terminal function furthermore comprises a first time slot counting means for counting time slots with parity error in the frames received from the switch terminating unit, and producing a result for each frame indicative of the number of parity errors of that frame. Means are provided for inserting each result indicative of the number of parity errors in a first available one of the test time slots in the frames sent to the switch terminating unit. The switch terminating unit furthermore comprises a second time slot counting means for counting time slots with parity error in the frames received from the terminal function and producing a result for each frame indicative of the number of parity errors for that frame. Parity fault monitoring functionality receives the result produced by the first time slot counting function and transferred in the test time slot, and the signal from the second time slot counting means indicative of test time slots appearing in the determined frame. Software associated with the monitoring functionality produces a result which is indicative of the number of parity faults received in test time slots minus the expected number of faults in the determined frames sent to the switch terminating unit.
Generally, and referring to the second aspect of the invention, to be able to detect and localize hardware faults in large systems, such as a telephony switch, there has to be functions in the hardware that can detect these faults. The functions can for example be implemented as parity checkers, checksums or comparison of data in redundant synchronous data flows, etc.
When a fault is found by some hardware, a flag is set or a counter is incremented. The flag or counter can then be read by software and further analysis can be made to localize the fault.
To be able to detect all faults in the hardware, it is a desire to be able to detect faults in the fault detection hardware, like the parity checkers and counters. Otherwise there might be a fault in a counter (e.g. it is stuck to 0) which is not detected since the software assumes that everything is correct as long as the value is 0.
It is a further object of the invention to provide, in accordance with the second aspect, a method and a system able to fulfil the above mentioned desire without disturbing the system in any way.
To attain this object the method according to the invention for detecting faults in fault detecting hardware designed to detect faults in a data flow, comprises the steps of introducing a known background load of faults in data flow, detecting actual background load of faults, and detecting a difference between the known and actual loads of faults.
The system according to the invention for detecting faults in fault detecting hardware designed to detect faults in a data flow comprises fault generating means for deliberately introducing faults in the data flow before it reaches the fault detecting hardware to obtain a known background load of faults in the data flow, fault counting means for counting actual faults including the deliberately introduced faults for detecting actual background load of faults, and software means for detecting a difference between the known and actual loads of faults.
The invention thus presents a solution on how to test fault detection hardware in a non intrusive way.
The way to accomplish this is by introducing such faults that the fault detection hardware will recognize these and count them, but the introduced faults must not in any way disturb the system. The software that is responsible for reading these counters, knows what the ‘background load’ of detected faults shall be. For approval the resulting value should be equal to the ‘background load’. If it is less or greater there is a fault.
By means of this principle, it is possible to find ‘normal’ faults, i.e. faults that the fault detection mechanism was supposed to detect. It is also possible to detect faults in the fault detection hardware and in the fault generating hardware.
REFERENCES:
patent: 4393490 (1983-07-01), Culley
patent: 4485467 (1984-11-01), Miles et al.
patent: 4532624 (1985-07-01), Renner
patent: 4546475 (1985-10-01), Sharpless et al.
patent: 4821256 (1989-04-01), Schmidt et al.
patent: 5367395 (1994-11-01), Yajima et al.
patent: 5455832 (1995-10-01), Bowmaster
patent: 5668801 (1997-09-01), Grunenfelder
patent: 5910977 (1999-06-01), Torregrossa
patent: 83/04355 (1983-12-01), None
patent: 9713390 (1998-06-01), None
Burns Doane Swecker & Mathis L.L.P.
Kizou Hassan
Telefonaktiebolaget L M Ericsson(publ)
Tran Thien
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