Rounding-off method and apparatus of floating point arithmetic a

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364745, G06F 738, G06F 750

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active

055684122

ABSTRACT:
An apparatus and method for arithmetic addition/subtraction of first and second floating point operands, each having a fraction portion and an exponent, includes an alignment circuit, an addition/subtraction-and-rounding-off circuit, and a normalization circuit. The alignment circuit aligns the fraction portions of the first and second operands based on a difference of their exponents obtained by comparing the respective exponents of the first and second operands. The addition/subtraction-and-rounding-off circuit performs at least two addition/subtraction operations between the aligned fraction portions of the first and second operands, and selectively outputs a result value of one of the addition/subtraction operations as a rounded-off result value in response to a rounding-off control signal so that the rounded-off result value is a rounded-off value of addition/subtraction of the fraction portions of the first and second operands. The normalization circuit normalizes the rounded-off result value to output a final result.

REFERENCES:
patent: 4562553 (1985-12-01), Mattedi et al.
patent: 4896286 (1990-01-01), Ueda
patent: 4926370 (1990-05-01), Brown et al.
patent: 5276634 (1994-01-01), Suzuki et al.

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