Rounding normalizer for floating point arithmetic operations

Details Rounding normalizer for floating point arithmetic operations Rounding normalizer for floating point arithmetic operations

1995-01-31

1996-08-27

Malzahn, David H.

Boots, shoes, and leggings

36471504, G06F 501, G06F 748

Patent

active

055507689

ABSTRACT:
A method and apparatus for parallel "normalize-round-normalize" floating point arithmetic. The rounding-normalizer of the invention receives as an input an infinitely precise mantissa which is the result of a floating point operation. This infinitely precise result mantissa is broken into two fields, the Close Enough Bits, and the Picky Bits. These bits are selectively passed to four parallel data paths for taking close enough bits and picky bits and producing a correctly rounded mantissa. The paths are, respectively; (a) a 1X.XX . . . X data path for mantissas greater than or equal to 2 but less than 4, the data path right shifting the upper bits and adjusting the exponent by +1 or +2; (b) a 01.XX . . . X data path for mantissas greater than or equal to 1 but less than 2, the data path right shifting the upper bits and adjusting the exponents by +0 or +1; (c) a 00.1X . . . X data path for mantissas greater than or equal to 1/2 but less than 1, the data path left shifting bits and adjusting the exponent by -1 or +0; and (d) a 00.01X . . . X data path for mantissas less than 1/2, the data path left shifting the bits and adjusting the exponent by the shift amount. Each of the data paths produces a normalized and rounded mantissa for its subset of mantissas.

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