Rounding mechanisms in processors

Details Rounding mechanisms in processors Rounding mechanisms in processors

2006-05-16

2006-05-16

Mai, Tan V. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S525000, C708S497000

Reexamination Certificate

active

07047272

ABSTRACT:
An arithmetic unit, for example a multiply and accumulate (MAC) unit42,for a processing engine includes a partial product reduction tree480.The partial product reduction tree will generate carry results and provides a final output to a final adder470connected to the partial production reduction tree. Unbiased rounding logic476is provided. A carry propagation tree is responsive to the carry results for anticipating a zero on each of N least significant bits of the final adder. When zero is anticipated on each of N least significant bits of the final adder, the carry propagation tree is operable to generate an output signal477which is used by the unbiased rounding stage to force the (N+1)th least significant bit of the final adder to zero. Through the use of a carry propagation tree to predict, or anticipate zeros on the N least significant bits, unbiased rounding can be effected without a time penalty in that a carry propagation tree can be configured to be at least a rapid as the carry propagation of the final adder. Where a zero anticipation function is provided, this can also be mapped onto the carry propagation tree, thus providing an efficient hardware implementation through sharing of that hardware between functions.

REFERENCES:
patent: 5128889 (1992-07-01), Nakano
patent: 5218563 (1993-06-01), Juri et al.
patent: 5561619 (1996-10-01), Watanabe
patent: 5581496 (1996-12-01), Lai
patent: 5586069 (1996-12-01), Dockser
patent: 5754458 (1998-05-01), Beraha et al.
patent: 6424955 (2002-07-01), Wong
patent: 0 469 841 (1992-02-01), None
TI-27677,A Bit Field Processor, co-filed as a regular application Oct. 1, 1999.
TI-27678,Rounding Mechanisms in Processors, co-filed as a regular application Oct. 1, 1999.
TI-27679,Linear Vector Computation, co-filed as a regular application Oct. 1, 1999.
TI-27680,Hardware Accelerator/Acceleration for Processing Systems, co-filed as a regular application Oct. 1, 1999.
TI-27681,Pipeline Protection, co-filed as a regular application Oct. 1, 1999.
TI-27682,Pipelined Hardware Stack, co-filed as a regular application Oct. 1, 1999.
TI-27683,A Processor With Conditional Execution of an Instruction Pair, co-filed as a regular application Oct. 1, 1999.
TI-27684,A Processor With Local Instruction Looping, co-filed as a regular application Oct. 1, 1999.
TI-27685,Compound Memory Access Instructions, co-filed as a regular application Oct. 1, 1999.
TI-27686,A Processor With a Computed Repeat Instruction, co-filed as a regular application Oct. 1, 1999.
TI-27688,A Processor With Apparatus for Verifying Instruction Parallelism, co-filed as a regular application Oct. 1, 1999.
TI-27689,Cache Miss Benchmarking, co-filed as a regular application Oct. 1, 1999.
TI-27690,A Processor With Apparatus for Indexed Branch During Instruction Iteration, co-filed as a regular application Oct. 1, 1999.
TI-27691,Circular Buffer Management, co-filed as a regular application Oct. 1, 1999.
TI-27700,Method and Apparatus for Accessing a Memory Core Multiple Times in a Single Clock Cycle, co-filed as a regular application Oct. 1, 1999.
TI-27757,Improved Multiplier Accumulator Circuits, co-filed as a regular application Oct. 1, 1999.
TI-27758,Zero Anticipation Method and Apparatus, co-filed as a regular application Oct. 1, 1999.
TI-27759,Trace FIFO Management, co-filed as a regular application Oct. 1, 1999.
TI-27760,Stack Pointer Management, co-filed as a regular application Oct. 1, 1999.
TI-27761,Software Breakpoint in a Delay Slot, co-filed as a regular application Oct. 1, 1999.
TI-27762,Cache Coherence During Emulation, co-filed as a regular application Oct. 1, 1999.
TI-27763,Memory Access Using Byte Qualifiers, co-filed as a regular application Oct. 1, 1999.
TI-27764,Dual Interrupt Vector Mapping, co-filed as a regular application Oct. 1, 1999.
TI-28234,Pipeline Protection, co-filed as a regular application Oct. 1, 1999.
TI-28433,Improvements in or Relating to Microprocessors, co-filed as a regular application Oct. 1, 1999.
Owen, R.;A Sub 10 Nanosecond Multiplier and Multiplier Accumulator, vol. 30, Nov. 18-20, 1986, pp. 14/5 1-5, N. Hollywood, US.
Hillman, G.D.;DSP56200: An Algorithm-Specific Digital Signal Processor Peripheral, Proc. Of the IEEE, vol. 75, No. 9, Sep. 1987, pp. 1185-1191.
Hokenek, E., et al.; Leading-Zero Anticopator (LZA) in the IBM RISC System/6000 Floating-Point Execution Unit, IBM Journal, Research and Development, 34(1990)Jan., No. 1, Armonk, NY, pp. 71-77.

Affiliated with

Also associated with

Rating

Rounding mechanisms in processors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Rounding mechanisms in processors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Rounding mechanisms in processors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3618312