Rounding adder for floating point processor

Details Rounding adder for floating point processor Rounding adder for floating point processor

1995-06-30

1997-12-02

Malzahn, David H.

Boots, shoes, and leggings

364748, G06F 750

Patent

active

056943504

ABSTRACT:
A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.

REFERENCES:
patent: 3316393 (1967-04-01), Ruthazer
patent: 5204832 (1993-04-01), Nakakura
patent: 5285406 (1994-02-01), Lynch et al.
patent: 5396445 (1995-03-01), Lal
patent: 5506800 (1996-04-01), Dao-Trong

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