Round increment in an adder circuit

Details Round increment in an adder circuit Round increment in an adder circuit

1998-08-28

2000-11-14

Malzahn, David H.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708505, G06F 750

Patent

active

061483141

ABSTRACT:
A floating point unit is described that performs addition operations. An adder 16 within the floating point unit receives a first input and a second input to generate a sum. This sum is subject to subsequent normalization by a normalizer 60 and rounding by an incrementer 64. If an operation is performed that is immediately followed by an addition operation using the result of the preceding operation, then the normalized but unrounded sum is fed back to the adder 16 together with an indication of its rounding requirement. This rounding requirement can be performed by the adder 16 in parallel with the execution of the following addition by using the carry-in bit of the adder 16 to apply any increment required to rounding of the preceding result.

REFERENCES:
patent: 4999802 (1991-03-01), Cocanougher et al.
patent: 5548544 (1996-08-01), Matheny et al.
patent: 5568412 (1996-10-01), Han et al.
patent: 5808926 (1998-09-01), Gorshtein et al.
patent: 5880984 (1999-03-01), Burchfiel et al.

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