Abrading – Precision device or process - or with condition responsive... – Computer controlled
Reexamination Certificate
1999-10-22
2002-04-30
Rachuba, M. (Department: 3724)
Abrading
Precision device or process - or with condition responsive...
Computer controlled
C451S283000, C451S287000, C451S288000
Reexamination Certificate
active
06379216
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, a chemical-mechanical polishing apparatus and method for planarizing the upper surfaces of semiconductor substrates.
2. Description of the Relevant Art
Fabrication of integrated circuits upon semiconductor substrates (“wafers”) involves numerous processing steps. For example, the fabrication of a metal-oxide-semiconductor (MOS) integrated circuit includes the formation of trench isolation structures within a semiconductor substrate to separate each MOS field-effect transistor that will be made. The semiconductor substrate is typically doped with either n-type or p-type impurities. A gate dielectric, typically composed of silicon dioxide, is formed on the semiconductor substrate. For each MOSFET being made, a gate conductor is formed over the gate dielectric and a source and drain are formed by introducing dopant impurities into the semiconductor substrate. Conductive interconnect lines are then formed to connect the MOSFETs to each other and to the terminals of the completed integrated circuit. Modern high-density integrated circuits typically include multiple interconnect levels to provide all of the necessary connections. Multiple interconnect levels are stacked on top of each other with intervening dielectric levels providing electrical insulation between interconnect levels.
During integrated circuit fabrication, unwanted elevational disparities of the upper surface of the semiconductor substrate that can occur after certain processing steps may have a detrimental effect on subsequent processing steps. For example, prior to formation of interconnect levels of an integrated circuit, a dielectric is deposited upon the transistors that have been formed on the semiconductor substrate. As deposited, this dielectric typically will not have a planar upper surface but will instead tend to conform to the underlying topography. If these elevational disparities are not removed, subsequent processing steps may suffer from a variety of problems. For instance, an interconnect metal deposited upon the non-planar upper surface of the dielectric may exhibit step coverage problems. Step coverage is an indication of how well a film conforms to an underlying step. If the interconnect metal is not deposited with sufficient step coverage, interconnect lines patterned from the interconnect metal may suffer from open circuit failure. A non-planar surface may also cause depth-of-focus problems for subsequent lithographically-patterned layers. Depth-of-focus refers to the ability of a lithographic systems to focus radiation on a photoresist only over a limited thickness. If a portion of the photoresist is at a different elevation than the rest of the photoresist due to a non-planar underlying surface, the elevationally disparate portion of the photoresist may not be fully exposed by the lithographic system resulting in a patterning of the photoresist different from the desired pattern.
Chemical-mechanical polishing (CMP) is a prevalent technique for planarizing surfaces of semiconductor substrates and thereby avoiding the problems discussed above. CMP removes surface material and planarizes surfaces through chemical and mechanical abrasion of surface material.
FIG. 1
illustrates a cross-sectional side view of a portion of a rotary CMP apparatus (“tool”) while
FIG. 2
illustrates a top view of the CMP tool. An example of a rotary CMP tool is the Auriga available from SpeedFam International, Inc. of Chandler, Ariz. Semiconductor wafer
10
is held in carrier
12
and is placed face down upon polishing pad stack
20
. Although four carrier/wafer assemblies
14
are shown in
FIG. 2
, polishing pad stack
20
may have one to six carrier/wafer assemblies placed upon it depending on the size of wafer
10
relative to the size of polishing pad stack
20
. Polishing pad stack
20
is affixed to platen
22
. Both carrier
12
and platen
22
may rotate and their rotational speeds are independently adjustable. A polishing fluid, typically a slurry, is deposited on the surface of polishing pad stack
20
through conduit
24
. The polishing slurry consists of an abrasive-particle-containing fluid that may be chemically reactive with one or more of the materials on the surface of the wafer. The polishing slurry occupies the interface between wafer
10
and polishing pad stack
20
.
During the polishing process, carrier
12
and platen
22
are rotated at angular frequencies &ohgr;
c
and &ohgr;
p
, respectively, while carrier
12
applies a force F downward on wafer
10
, typically referred to as “down force”. The polishing slurry chemically reacts with the surface material of wafer
10
while the movement of wafer
10
relative to polishing pad stack
20
causes the abrasive particles contained in the polishing slurry to strip the reacted material from wafer
10
. The amount of material removed by CMP is governed by several variables including down force, carrier rotational speed, platen rotational speed, polishing time, and composition of the polishing fluid.
Polishing pad stack
20
includes polishing pad
16
and polishing pad
18
affixed to platen
22
. Polishing pad
16
is preferably harder than polishing pad
18
. Platen
22
provides rigid support for polishing pad stack
20
. A typical pad stack used on CMP tools is an IC1000 stacked on top of a Suba IV. Both pads are manufactured by Rodel, Inc. of Phoenix, Ariz. Multiple pads are typically used to simultaneously improve both local flatness and global uniformity of the polished wafer. A problem with polishing pad stack
20
is that replacement of worn out pads is time consuming. Replacing pads requires that pads
16
and
18
be removed from platen
22
and then new pads must be affixed to platen
22
. During the replacement process, the CMP tool is not available for use thereby increasing manufacturing costs.
FIG. 3
shows a portion of a wafer, which includes semiconductor substrate
30
, in contact with polishing pad stack
20
. Layer
32
, which has surface irregularities that are to be removed, has been previously formed upon semiconductor substrate
30
. Elevationally raised area
34
is in contact with hard polishing pad
16
which is attached to soft polishing pad
18
. Polish pad
16
has deformed slightly and projects in toward elevationally depressed area
36
. The harder polish pad
16
is, the less it will deform. The ideal CMP process would only remove material from elevationally raised area
34
and not from elevationally depressed area
36
and would result in surface
38
of layer
32
after polishing. Realistically, some material is removed from elevationally depressed area
36
; however, material is removed at a higher rate from elevationally raised area
34
such that surface
40
results after polishing. Layer
32
has an average thickness t after polishing. In general, the flatness and location of actual polished surface
40
is desired to be as similar as possible to ideal polished surface
38
.
It is also desired for surface
40
of the polished wafer to have good uniformity, which can be defined as average thickness t of layer
32
being the same at all locations on semiconductor substrate
30
. Softer polishing pad
18
is placed underneath harder polishing pad
16
to improve uniformity of the polished wafer. Softer polishing pad
18
allows polishing pad stack
20
to partially conform to minor changes in the overall shape of the wafer. For instance, if semiconductor substrate
30
is slightly bowed, the polishing pad stack will also be slightly bowed so it can remain in contact with the wafer over its entire surface while the use of hard polishing pad
16
as the top polishing pad minimizes conformance of the polishing pad stack to local surface irregularities that are to be removed. In general, the CMP process parameters include a low down force, a high rotational speed, and a hard polishing pad to improve uniformity. Better uniformity generally results in increased yield, which is defined a
Advanced Micro Devices , Inc.
Conley & Rose & Tayon P.C.
Daffer Kevin L.
Rachuba M.
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