ROM With redundant ROM cells employing a highly resistive polysi

Details ROM With redundant ROM cells employing a highly resistive polysi ROM With redundant ROM cells employing a highly resistive polysi

1980-12-15

1983-09-13

Davie, James W.

357 23, 357 41, 357 51, 357 58, H01L 2904, H01L 2912, H01L 2978, H01L 2702

Patent

active

044045816

ABSTRACT:
The present invention comprises a unique FET with resistor in its drain lead of undoped polysilicon which may be characterized by high resistance in the absence of the application of a biasing voltage across the FET and the resistor when the FET is conducting, which biasing voltage irreversibly changes the resistor to a high state of conductivity thereby selectively providing the two logic states. This device may comprise a redundant cell for a ROM memory and may be uniquely fabricated utilizing VLSI MOS processing steps to provide a new manufacturing process.

REFERENCES:
patent: 4231051 (1980-10-01), Ceistode et al.
patent: 4297721 (1981-10-01), McKenny et al.
T. H. Ning, "Polysilicon Resistor Process for Bipolar and MOS applications", IBM Technical Disclosure Bulletin, vol. 23, (1980) pp. 368-370.

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