ROM with a reduced static consumption

Details ROM with a reduced static consumption ROM with a reduced static consumption

2000-05-12

2002-03-26

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Read only systems

Semiconductive

C365S189070, C365S182000, C365S230030

Reexamination Certificate

active

06363001

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a ROM structure, the static consumption of which is decreased by an inversion of the cell programming according to the relation between the number of programmed cells and the number of unprogrammed cells.
2. Discussion of the Related Art
FIG. 1
schematically shows a conventional ROM structure. It includes a plurality of memory cells
10
arranged in rows and columns. The cells
10
of each row are selected by a respective word line W, and a selected cell presents its data on a bit line BL common to the cells of the same column.
Each bit line BL is connected to a high supply potential Vdd via a respective P-channel MOS precharge transistor MP. All precharge transistors MP are controlled by a common precharge line P.
Further, bit lines BL are connected to sense amplifiers
12
. Generally, the bit lines are grouped in several sets, each set being associated with a single sense amplifier
12
via a multiplexer
14
. Each multiplexer
14
selects the bit line of the set to be provided to the amplifier according to the read address presented to the memory.
As shown, the programmed cells
10
include an N-channel MOS transistor MN connected between the corresponding bit line and the low supply potential, while the unprogrammed cells
10
include no transistor. The transistors MN of the cells of a same row are all controlled by the corresponding word line W.
With recent integrated circuit manufacturing technologies, transistors become smaller and smaller but have greater and greater leakages. As a result, the static consumption of the circuits formed by means of these technologies tends to increase if no particular precautions are taken. The static consumption of a circuit is particularly disturbing in devices supplied by a battery.
In the memory of
FIG. 1
, even if no transistor is turned on, for example in a stand-by mode, there nevertheless exists a leakage current path between high potential Vdd and the low potential via each precharge transistor MP and each transistor MN of the same column. The static consumption is proportional to the number of transistors MN in the memory, that is, to the number of programmed cells.
To reduce the static consumption, it has been devised to invert the programming of the entire memory when the number of cells that would normally be programmed is greater than the number of cells that would normally not be programmed. Of course, the memory outputs, that is, the outputs of sense amplifiers
12
, are then inverted to restore the required logic levels.
A static consumption that is always lower than half that of a memory in which all cells would be programmed is thus obtained.
A disadvantage of this solution, given that it may be assumed that the cells are programmed according to a random law, that in average, 50% of the cells are programmed. The obtained consumption gains thus correspond to the variations around this average value and are insignificant, except in very specific cases.
U.S. Pat. No. 5,745,401 claims that each column of cells may be programmed in a conventional programming mode or in an inverted programming mode. This could cause a substantial consumption gain. However, patent '401 also claims the use of a decoder adapted to record whether each column is programmed in the conventional programming mode or in the inverted programming mode. Such a decoder increases the surface of the circuit and its access time.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a ROM structure enabling significant reduction of the static consumption, without increasing the surface and the access time of the structure.
To achieve this object, an embodiment of the present invention provides a ROM including memory cells, of which those that are programmed are formed of a transistor connected between a bit line and a supply potential, the cells being organized in sets of at least one column coupled to one sense amplifier per set. The cell programming is inverted with respect to a desired programming only in specific sets where the desired programming would result in a number of programmed cells greater than the number of unprogrammed cells, the logic state provided by the sense amplifiers associated with the specific sets being inverted. Each sense amplifier is formed of at least two stages interconnected by two differential lines, the differential lines being interchanged for the sense amplifiers associated with the specific sets.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.


REFERENCES:
patent: 4426686 (1984-01-01), Yamamoto et al.
patent: 5477484 (1995-12-01), Nakashima
patent: 5703820 (1997-12-01), Kohno
patent: 5745401 (1998-04-01), Lee
patent: 5787033 (1998-07-01), Maeno
patent: 5930180 (1999-07-01), Callahan
patent: 0 040 045 (1981-11-01), None

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