ROM/PLA Structure and method of testing

Details ROM/PLA Structure and method of testing ROM/PLA Structure and method of testing

1982-03-01

1984-07-17

Atkinson, Charles E.

Excavating

324 73R, G01R 3128

Patent

active

044610009

ABSTRACT:
An improved integrated ROM/PLA structure which is capable of simultaneous PLA and ROM addressing substantially reduces the number of tests needed to verify the complete structure. The OR gate matrix and the ROM addressing mode of the AND gate matrix are verified using the ROM addressing mode. The PLA addressing mode is tested by the simultaneously using the ROM and PLA addressing modes to individually activate the AND gates. The AND gates are then tested with the DON'T CARE address lines at a first state and then a second logic state. The test sequence then includes complementing the CARE lines one at a time.
The ROM/PLA structure is also improved to include two input structures providing parallel inputs to the OR matrix and dedicated first and second ROM portions of the OR matrix. The output logic is modified so as to merge the literal from the input macroinstruction into the output microinstruction. Similarly, an improved next address logic is provided such that the next address is a function of the output of the OR gate, the microinstruction input, the current computer status and test word input.

REFERENCES:
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patent: 3982111 (1976-09-01), Lerner et al.
patent: 3987287 (1976-10-01), Cox et al.
patent: 4024386 (1977-05-01), Caudel et al.
patent: 4055754 (1977-10-01), Chesley
patent: 4124899 (1978-11-01), Birkner et al.
patent: 4140967 (1979-02-01), Balasubramanian et al.
Pilost, D., et al., "Latched Inputs-An Improvement to PLA," IBM Technical Disclosure Bulletin, vol. 20, No. 11A, Apr. 1978, 4438-4439.

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